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phase locked loops (14) 14
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Electronics Letters, ISSN 0013-5194, 3/2018, Volume 54, Issue 5, pp. 321 - 322
Journal Article
IEEE Transactions on Signal Processing, ISSN 1053-587X, 08/2001, Volume 49, Issue 8, pp. 1808 - 1815
Journal Article
IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 09/2006, Volume 53, Issue 9, pp. 1896 - 1908
Journal Article
2012 IEEE 11th International Conference on Signal Processing, ISSN 2164-5221, 10/2012, Volume 1, pp. 119 - 122
This paper presents the design and simulation of an Adaptive receiver structure using the Normalized Least-mean-square (NLMS) for impulsive noise reduction in... 
NLMS | adaptive receivers | Impulsive noise | Adaptive receivers
Conference Proceeding
2011 18th IEEE International Conference on Electronics, Circuits, and Systems, 12/2011, pp. 73 - 76
This paper proposes an adaptive technique for rapid error correction of a digital tanlock loop architecture with no time delay (ANDTL) unit and with a... 
Delay effects | Noise | Linearity | Frequency shift keying | Jitter | Frequency estimation | Phase locked loops
Conference Proceeding
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 12/2013, pp. 881 - 884
This paper proposes an efficient demodulator for multiple frequency shift keying (MFSK) signals using a modified version of the time delay tanlock loop (TDTL)... 
Smoothing methods | Delay effects | Bit error rate | Frequency shift keying | Steady-state | Phase locked loops | Demodulation | Acquisitions | Smoothing | Circuits | Demodulators | Electronics | Tools | Marketing | Matlab
Conference Proceeding
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 12/2012, pp. 909 - 912
This paper proposes an improved time delay digital tanlock loop (TDTL) system in which a feedforward loop is used to initialize the loop filter memory so as to... 
Delay effects | Frequency shift keying | Frequency estimation | Steady-state | Digital filters | Phase locked loops | Field programmable gate arrays
Conference Proceeding
2011 IEEE EUROCON - International Conference on Computer as a Tool, 04/2011, pp. 1 - 4
This paper presents the architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source... 
Photovoltaic systems | grid synchronization | Renewable energy resources | PV generator | Inverters | Generators | time-delay tanlock loop | Synchronization | Oscillators | phase lock loop
Conference Proceeding
2008 International Symposium on Telecommunications, 08/2008, pp. 73 - 76
This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) to linearize the phase difference detection,... 
zero crossing DPLL | non-uniform sampling | Frequency shift keying | Digital signal processing | Detectors | digital phase locked loops | Steady-state | Phase locked loops | Gain | Equations | Non-uniform sampling | Zero crossing DPLL | Digital phase locked loops
Conference Proceeding
2010 17th IEEE International Conference on Electronics, Circuits and Systems, 12/2010, pp. 475 - 478
A new technique for fast error correction of the TDTL (time delay digital tanlock loop) is proposed. The technique is based on early comparison of the input... 
Time frequency analysis | OFDM | Oscillators | Frequency shift keying
Conference Proceeding
Sensor Signal Processing for Defence (SSPD 2011), 2011, Volume 2011, Issue 4, p. 15
In this paper the architecture of a second-order time delay digital tanlock loop (TDTL) with real-time adaptive calculation of the loop filter coefficients is... 
Modulators, demodulators, discriminators and mixers | Digital filters | Interpolation and function approximation (numerical analysis) | loop filter coefficients | recursive leased squares algorithm | adaptive filter | TDTL
Conference Proceeding
2011 IEEE EUROCON - International Conference on Computer as a Tool, 04/2011, pp. 1 - 4
A dual Time Delay Digital Tanlock Loop (D-TDTL) topology is proposed in this work. The system consists of a stacked dual loop of which the top one acts as a... 
Frequency locked loops | Phase noise | PLL | Frequency shift keying | FLL | Jitter | AWGN and Jitter | Dual loop | Phase locked loops | Digital filters | TDTL | FSK
Conference Proceeding
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 12/2009, pp. 555 - 558
This paper presents a time delay digital tanlock loop with a linearized phase detector (TDTL-LPD) architecture. This is achieved through replacement of the... 
Programmable control | Delay effects | Detectors | Frequency shift keying | Control systems | Error correction | Adaptive control | Phase detection | Oscillators | Demodulation
Conference Proceeding
2010 IEEE Sarnoff Symposium, 04/2010, pp. 1 - 5
This paper presents a second order time delay digital tanlock loop with improved locking as well as acquisition performance. The former is achieved through... 
System testing | Delay effects | Digital-controlled oscillators | Digital filters | Phase detection | lock range | TDTL | Digital control | PLL | Frequency shift keying | Detectors | Sampling methods | Error correction | acquisition | FSK | Lock range | Acquisition
Conference Proceeding
TENCON 2005 - 2005 IEEE Region 10 Conference, ISSN 2159-3442, 11/2005, Volume 2007, pp. 1 - 4
The main objective of this paper is to broaden the lock range of the Digital Tanlock Loop (DTL) by extending the stable behaviour of the loop to larger control... 
Chaos | Tracking loops | Filters | Communication system control | Detectors | Bifurcation | Frequency | Sampling methods | Phase locked loops | Phase detection
Conference Proceeding
2010 7th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP 2010), 07/2010, pp. 368 - 372
This paper presents a novel design of a digital phase lock loop based on the digital tanlock loop (DTL) architecture. The new simplified design eliminates the... 
Delay effects | Phase locked loops | Frequency control | Frequency shift keying | Detectors | Demodulation
Conference Proceeding
2007 9th International Symposium on Signal Processing and Its Applications, 02/2007, pp. 1 - 4
This paper presents a system with auto selection technique to reduce impulsive noise effect in wireless communication systems. The impulsive noise is detected... 
Noise figure | Gaussian noise | Working environment noise | Noise reduction | Electromagnetic interference | Frequency shift keying | Frequency estimation | Noise generators | Field programmable gate arrays | Signal to noise ratio
Conference Proceeding
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 12/2006, pp. 1516 - 1519
A frequency synthesizer using a first-order time delay tanlock loop (TDTL) is proposed in this work. The synthesizer involves introducing an integer divider... 
Digital control | Frequency synthesizers | Delay effects | Circuits | Signal processing | Frequency conversion | Sampling methods | Educational institutions | Digital-controlled oscillators | Equations
Conference Proceeding
2007 IEEE International Conference on Signal Processing and Communications, 11/2007, pp. 656 - 659
An enhanced frequency synthesizer using a first order time delay tanlock loop (TDTL) is proposed in this work. Two adaptation mechanisms are introduced to... 
Frequency synthesizers | System testing | Target tracking | Delay effects | Educational institutions | TDTL | System performance | Signal processing | Frequency | Signal synthesis | Synthesizer | Gain | Signal detection
Conference Proceeding
2010 7th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP 2010), 07/2010, pp. 373 - 376
This paper proposes two circuit topologies for acquisition enhancement in a time delay digital tanlock loop (TDTL). They are based on feedforward (FF) and... 
Delay effects | Detectors | Steady-state | Phase locked loops | Integrated circuit modeling | Oscillators | Frequency control
Conference Proceeding
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