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IEEE Transactions on Electron Devices, ISSN 0018-9383, 10/2017, Volume 64, Issue 10, pp. 4002 - 4010
Journal Article
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 10/2019, Volume 66, Issue 10, pp. 2196 - 2206
This article presents an energy-efficient triple-node-upset (TNU)-tolerant latch in a subthreshold/near-threshold regime. The proposed latch provides the TNU... 
Semiconductor device modeling | energy efficient latch | Latches | Radiation hardening (electronics) | radiation hardening | triple-node upset (TNU) | soft error | Logic gates | Circuit reliability | CMOS technology | Energy efficiency | Transistors
Journal Article
Integration, ISSN 0167-9260, 05/2019, Volume 66, pp. 119 - 127
Energy efficiency is considered to be the most critical design parameter for IoT and other ultra low power applications. However, energy efficient circuits... 
Radiation hardening latch | Soft error | Single event upset (SEU) | Energy efficient latches | Transient fault | Radiation hardening | Latches | Design parameters | Circuits | Soft errors | Internet of Things | Immunity | CMOS | Low voltage | Power management | Energy efficiency | Threshold voltage | Energy management
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 12/2019, Volume 66, Issue 12, pp. 5065 - 5071
Due to the highly variation-prone nature of the near-threshold voltage (NTV) circuits, it is critical to have design and performance models that consider... 
process | Computational modeling | and temperature (PVT) variation | Inverters | Digital buffer | voltage | near-threshold regime | effective current | Miller effect | Capacitance | FinFETs | Delays | Integrated circuit modeling | ring oscillator | fin-shaped field-effect transistors (FinFETs) | PHYSICS, APPLIED | ENGINEERING, ELECTRICAL & ELECTRONIC | CMOS | FINFETS | DELAY MODEL
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 02/2017, Volume 64, Issue 2, pp. 629 - 633
This brief investigates for the first time, a method to extract the value of saturation drain voltage for a tunnel FET. The saturation in output... 
TFETs | analog performance | nanowire TFET | Doping | V DSAT extraction technique">V DSAT extraction technique | Logic gates | Tunneling | Analog circuits | Capacitance | Amplifier design | drain current saturation | Extraction procedures
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 02/2017, Volume 64, Issue 2, pp. 629 - 633
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 11/2017, Volume 64, Issue 11
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 01/2017, Volume 64, Issue 1, p. 629
Journal Article
IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 06/2014, Volume 61, Issue 6, pp. 1714 - 1726
Strain engineering for performance enhancement is an integral part of a state-of-the-art CMOS process flow. However, use of stressors makes the performance of... 
Delay model | Discharges (electric) | Inverters | eSiGe/C | variability | Stress | Analytical models | HSPICE | TCAD | t/c-ESL | Delays | Mathematical model | process-induced mechanical stress | Load modeling | CMOS | PITCH OPTIMIZATION | Delaymodel | STRAIN | processinduced mechanical stress | ENGINEERING, ELECTRICAL & ELECTRONIC | Circuit design | Mathematical analysis | Nanostructure | Devices | Delay | Strain
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 09/2019, Volume 27, Issue 9, pp. 2170 - 2179
Near-threshold voltage (NTV) digital VLSI circuits, though important, have their sequential elements vulnerable to soft errors. The critical charge for a... 
Energy-efficient latches | Latches | Computational modeling | Single event upsets | soft error | radiation hardening latch | SPICE | Transistors | Transient analysis | Load modeling | single event upsets (SEU) | IMPACT | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | SUBTHRESHOLD SRAM | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 11/2012, Volume 59, Issue 11, pp. 3120 - 3123
Journal Article
半导体学报:英文版, ISSN 1674-4926, 2015, Volume 36, Issue 1, pp. 76 - 81
A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an... 
MOSFET | 场效应晶体管 | 电子密度 | 栅极电压 | 表面电位 | 费米 | 通道 | 隧道电流 | Channel properties | Electron quasi-Fermi potential | I-V characteristics | Resistive drop | Si-DG TFET | Drain extension regime resistance | Electric potential | Semiconductors | Simulation | Drains | Voltage | Devices | Channels | Gates
Journal Article
IEEE Transactions on Nanotechnology, ISSN 1536-125X, 11/2017, Volume 16, Issue 6, pp. 965 - 973
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 03/2016, Volume 63, Issue 3, pp. 1392 - 1396
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 07/2019, Volume 66, Issue 7, pp. 2863 - 2868
Journal Article
IEEE Transactions on Circuits and Systems II: Express Briefs, ISSN 1549-7747, 12/2019, pp. 1 - 1
This paper presents a general approach for generating high-frequency multiphase signals (even/odd), low phase noise, low power, and reduced supply sensitivity... 
single-ended ring oscillator | skewed-delay | low power | Even/odd multiphase signal generation | supply sensitivity | phase noise | multi-loop
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 01/2018, Volume 65, Issue 1, pp. 322 - 330
Journal Article
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