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IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 04/2019, Volume 66, Issue 4, pp. 1643 - 1656
Journal Article
Microprocessors and Microsystems, ISSN 0141-9331, 11/2018, Volume 63, pp. 216 - 225
Journal Article
Journal of Circuits, Systems and Computers, ISSN 0218-1266, 2017, Volume 26, Issue 6
Most digit-recurrence algorithms for division, such as the Sweeney-Robertson-Tocher (SRT) algorithm, have been used in order to take advantage of the redundant... 
Digital arithmetic | carry-save addition | redundant representation | digit-recurrence division | SRT division | DESIGN | SQUARE | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | DIGIT SELECTION | DIVISION | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 03/2018, Volume 26, Issue 3, pp. 508 - 521
Journal Article
Journal Article
IET Computers and Digital Techniques, ISSN 1751-8601, 07/2014, Volume 8, Issue 4, pp. 187 - 187
Floating-point (FP) multiply-add fused and multiply-accumulate represent the most common arithmetic operation in a wide range of applications, such as graphic... 
Multimedia | Construction | Digital techniques | Digital signal processing | Floating point arithmetic | Filled plastics | Cost engineering | Field programmable gate arrays
Journal Article
IET Computers & Digital Techniques, ISSN 1751-8601, 7/2014, Volume 8, Issue 4, pp. 187 - 197
Floating-point (FP) multiply-add fused (F1*F2 ± F3) and multiply-accumulate represent the most common arithmetic operation in a wide range of applications,... 
HIGH-PERFORMANCE | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | FPGA IMPLEMENTATION | DOT-PRODUCT | LATENCY | COMPUTER SCIENCE, THEORY & METHODS | UNITS
Journal Article
Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, 5/2016, Volume 87, Issue 2, pp. 169 - 180
Journal Article
2016 Euromicro Conference on Digital System Design (DSD), 08/2016, pp. 244 - 251
This paper proposes multi-domain quantization for a partially-parallel QC-LDPC decoder, which allows efficient memory bandwidth utilization. The change of... 
Forward error correction | Throughput | Quantization (signal) | Decoding | Energy resolution | Iterative decoding | Degradation | Messages | Architecture | Quantization | Electronics | Channels | Decoders
Conference Proceeding
Microelectronics Reliability, ISSN 0026-2714, 2010, Volume 50, Issue 2, pp. 304 - 311
This paper presents a VHDL-based simulated fault injection (SFI) methodology for quantum circuits. The main objective is to attain a high error modeling... 
Journal Article
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), ISSN 0302-9743, 2016, Volume 9637, pp. 277 - 289
Conference Proceeding
2016 24th Telecommunications Forum (TELFOR), 11/2016, pp. 1 - 4
This paper proposes a QC-LDPC partial parallel architecture that implements a hard decision message passing algorithm based on Gallager-B decoding. The... 
Hard Decision | Memory management | FPGA | LDPC | Throughput | Decoding | Iterative decoding | Field programmable gate arrays | Forward Error Correction
Conference Proceeding
Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, ISSN 2159-3469, 09/2016, Volume 2016-, pp. 697 - 700
Conference Proceeding
2019 22nd Euromicro Conference on Digital System Design (DSD), 08/2019, pp. 96 - 101
In this paper, we present a parametric hardware accelerator for Takagi-Sugeno fuzzy controllers. The architecture consists of an application specific weighting... 
Fuzzy control | Process control | FPGA acceleration | Manipulators | Hardware | Registers | Takagi-Sugeno model | Field programmable gate arrays | robot arm control
Conference Proceeding
Microelectronics Reliability, ISSN 0026-2714, 02/2010, Volume 50, Issue 2, pp. 304 - 311
This paper presents a VHDL-based simulated fault injection (SFI) methodology for quantum circuits. The main objective is to attain a high error modeling... 
NANOSCIENCE & NANOTECHNOLOGY | PHYSICS, APPLIED | ENGINEERING, ELECTRICAL & ELECTRONIC | Integrated circuits | Analysis | Complementary metal oxide semiconductors | Semiconductor chips
Journal Article
2018 21st Euromicro Conference on Digital System Design (DSD), 08/2018, pp. 104 - 109
Non-Surjective Finite Alphabet Iterative Decoding (NS-FAID) represents an LDPC decoding algorithm that uses reduced message storage, with similar or improved... 
Quantization (signal) | Multiprocessor interconnection | FPGA | Forward error correction | LDPC | Hardware | parity check | Decoding | Iterative decoding | Parity check
Conference Proceeding
2014 24th International Conference on Field Programmable Logic and Applications (FPL), ISSN 1946-147X, 09/2014, pp. 1 - 4
This paper proposes a FPGA implementation based on sliding processing window for Harris corner algorithm. It represents one of the most frequently used... 
Smoothing methods | Harris's algorithm | Buffer storage | Image processing | Pipelines | Computer architecture | corner detection | Field programmable gate arrays | Clocks
Conference Proceeding
2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 10/2017, Volume 2017-, pp. 1 - 5
This paper proposes cost efficient very high throughput layered decoding architecture for array quasi-cyclic Low-Density Parity-Check (QC-LDPC) codes,... 
Quantization (signal) | LDPC Decoding | Throughput | Layered Scheduling | Hardware | Decoding | Table lookup | NS-FAID | Iterative decoding | Forward Error Correction
Conference Proceeding
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