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2005, 2. Aufl., ISBN 9780387262321
Currently employed at STMicroelectronics, Transactional-Level Modeling (TLM) puts forward a novel SoC design methodology beyond RTL with measured improvements... 
eBook
01/2005, ISBN 9781280459610
Annotation Currently employed at STMicroelectronics, Transactional-Level Modeling (TLM) puts forward a novel SoC design methodology beyond RTL with measured... 
Web Resource
04/2017
Techniques are disclosed to adaptively control an image sensor and image signal processor (ISP), collectively known as an image pipeline, such that a minimum... 
ELECTRIC COMMUNICATION TECHNIQUE | PICTORIAL COMMUNICATION, e.g. TELEVISION | ELECTRICITY
Patent
2005, ISBN 9780387262321
Book Chapter
06/2016
Techniques are disclosed to adaptively control an image sensor and image signal processor (ISP), collectively known as an image pipeline, such that a minimum... 
ELECTRIC COMMUNICATION TECHNIQUE | PICTORIAL COMMUNICATION, e.g. TELEVISION | ELECTRICITY
Patent
Proceedings of the 5th IEEE/ACM international conference on hardware/software codesign and system synthesis, 09/2007, pp. 215 - 216
System architects working on SoC design have traditionally been hampered by the lack of a cohesive methodology for architecture evaluation and co-verification... 
performance | SoC | SystemC | verification | Real time systems | Bridges | Analytical models | Computer architecture | Generators | Filling | Verification | System-on-a-chip | Performance
Conference Proceeding
2005, ISBN 9780387262321
The trend of “the smaller the better” in semiconductor industry pictures a bright future for System-on-Chip (SoC). The full exploitation of new silicon... 
SoC bottleneck | system-to-RTL design flow | Electronics and Microelectronics, Instrumentation | Optical and Electronic Materials | abstraction level | Engineering Design | Electronic and Computer Engineering | OSCI | Engineering | TLM | transaction level modeling | integrated circuit | system-on-chip | SystemC
Book Chapter
Book Chapter
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006, 2006, pp. 85 - 90
The authors present a technique to synchronize between PSL (property specification language) checkers and SystemC IPs at the highest abstraction level of the... 
Runtime | Object oriented modeling | Computer bugs | Laboratories | Hardware | Microelectronics | Specification languages | Synchronization | Consumer electronics | Clocks | Assertion Based Verification (ABV) | PSL sampling or clocking | Property Specification Language (PSL) | Transaction Level Modeling (TLM)
Conference Proceeding
Proceedings of the conference on design, automation and test in europe, 02/2004, Volume 1, p. 10122
There is tremendous interest in design languages these days - and more particularly, SystemC and SystemVerilog. Sometimes the truth about design languages can... 
Conference Proceeding
Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe - Volume 1; 16-20 Feb. 2004, 02/2004
There is tremendous interest in design languages these days - and more particularly, SystemC and SystemVerilog. Sometimes the truth about design languages can... 
Conference Proceeding
Proceedings Design, Automation and Test in Europe Conference and Exhibition, ISSN 1530-1591, 2004, Volume 1, pp. 122 - 127 Vol.1
There is tremendous interest in design languages these days - and more particularly, SystemC and SystemVerilog. Sometimes the truth about design languages can... 
Productivity | Encapsulation | Electronic design automation and methodology | Design automation | Clouds | Automatic testing | Europe | Microelectronics | Computer science education | Hardware design languages
Conference Proceeding
Proceedings of the conference on design, automation and test in europe, 03/2003, Volume 1, p. 10876
Complex systems on chip (SoCs) present challenges in the design and verification process that cannot be adequately addressed by traditional methodologies based... 
Conference Proceeding
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