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Applied Physics A, ISSN 0947-8396, 6/2009, Volume 95, Issue 4, pp. 989 - 997
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 05/1996, Volume 31, Issue 5, pp. 677 - 688
This paper describes an analytical model for the access and cycle times of on-chip direct-mapped and set-associative caches. The inputs to the model are the... 
Wiring | Analytical models | Costs | Councils | Stacking | Delay estimation | Computer architecture | Decoding | Equations | Driver circuits | MEMORIES | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Proceedings of the 42nd Annual IEEE/ACM International Symposium on microarchitecture, ISSN 1072-4451, 12/2009, pp. 469 - 480
This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and... 
Semiconductor device modeling | Out of order | Costs | Electronic design automation and methodology | Microarchitecture | Multicore processing | Integrated circuit interconnections | Predictive models | Verification | Timing | Space exploration | Performance | C.0 [computer systems organizations]: general
Conference Proceeding
Computer, ISSN 0018-9162, 11/2005, Volume 38, Issue 11, pp. 32 - 38
Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating... 
IEEE news | Costs | Portable computers | Multicore processing | Multiprocessors | Power-aware computing | CMP | Throughput | Sun | Heterogeneity | Microprocessors | Moore's Law | Multicore microprocessors | Frequency | Chip multiprocessors | System architectures | Clocks | COMPUTER SCIENCE, SOFTWARE ENGINEERING | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | Usage | Analysis | Multiprocessor | Law | Asymmetry | Chips
Journal Article
Proceedings of the 35th Annual International Symposium on computer architecture, ISSN 1063-6897, 06/2008, pp. 153 - 164
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this... 
Nanophotonics, Many-core CMP, On-chip Networks, 3D stacking | Costs | Wavelength division multiplexing | 3D stacking | Nanophotonics | Microprocessors | On-chip Networks | Power system interconnection | Wires | Bandwidth | Many-core CMP | Corona | Silicon | Nanoscale devices | Impedance
Conference Proceeding
IEEE Computer Architecture Letters, ISSN 1556-6056, 01/2003, Volume 2, Issue 1, pp. 2 - 2
This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing... 
Computer science | Energy consumption | Fans | Costs | low-power architecture | Computer architecture | Packaging | chip multiprocessor | Power dissipation | System software | Application software | Power engineering and energy | Consumption | Reduction | Microprocessors | Chips | Dissipation | Software | Cost engineering | Computer programs
Journal Article
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, ISSN 1072-4451, 12/2003, Volume 2003-, pp. 81 - 92
This paper proposes and evaluates single-ISA heterogeneousmulti-core architectures as a mechanism to reduceprocessor power dissipation. Our design... 
Computer science | Energy consumption | Computer architecture | Frequency | Power dissipation | System software | Application software | Clocks | Power engineering and energy | Milling machines
Conference Proceeding
Proceedings of the 2009 International Conference on computer-aided design, ISSN 1092-3152, 11/2009, pp. 269 - 275
Phase-change random access memory (PCRAM) is an emerging memory technology with attractive features, such as fast read access, high density, and... 
Computer science | Bridges | Nonvolatile memory | Space technology | Random access memory | Predictive models | Phase change random access memory | Power system modeling | Power engineering and energy | System-level design
Conference Proceeding
2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, ISSN 1550-5774, 10/2009, pp. 379 - 379
The combination of decreasing device reliability due to deep submicron scaling, increasing integration, and the size of future exascale high-performance... 
checkpointing | Technological innovation | Cloud computing | Very large scale integration | isolation | Resilience | duplication | Microprocessors | Fault tolerant systems | Computer architecture | CMOS technology | exascale systems | Timing | Power system reliability
Conference Proceeding
Proceedings of the 35th Annual International Symposium on computer architecture, ISSN 1063-6897, 06/2008, pp. 51 - 62
In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main... 
LLC, CACTI, cache, SRAM, commodity DRAM, logic-process based DRAM | LLC | cache | Multicore processing | Circuits | Stacking | Random access memory | Application software | SRAM | Fabrication | CACTI | Computer architecture | Bandwidth | logic-process based DRAM | commodity DRAM | Logic | Propagation delay
Conference Proceeding
Proceedings of the 31st annual international symposium on computer architecture, ISSN 1063-6897, 03/2004, Volume 31, pp. 64 - 75
A single-ISA heterogeneous multi-core architecture is achip multiprocessor composed of cores of varying size, performance,and complexity. This paper... 
Computer science | Multithreading | Microprocessors | Computer architecture | Parallel processing | Performance gain | Throughput | Yarn | Delay | Milling machines
Conference Proceeding
IEEE Computer Architecture Letters, ISSN 1556-6056, 01/2009, Volume 8, Issue 1, pp. 5 - 8
Journal Article
[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture, ISSN 0149-7111, 1990, pp. 364 - 373
Hardware techniques for improving the performance of caches are presented. Miss caching places a small, fully associative cache between a cache and its refill... 
Costs | Reduced instruction set computing | Prefetching | Technology forecasting | Hardware | Performance loss | Application software | Delay
Conference Proceeding
Computer, ISSN 0018-9162, 06/2007, Volume 40, Issue 6, pp. 49 - 59
Journal Article
Computer, ISSN 0018-9162, 09/1991, Volume 24, Issue 9, pp. 18 - 29
The interaction between computer architecture and IC technology is examined. To evaluate the attractiveness of particular technologies, computer designs are... 
Integrated circuit technology | Computer aided instruction | Fault tolerance | Costs | Cooling | Working environment noise | Computer architecture | Environmental factors | Central Processing Unit | Clocks | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | COMPUTER SCIENCE, SOFTWARE, GRAPHICS, PROGRAMMING
Journal Article
2008 16th IEEE Symposium on High Performance Interconnects, ISSN 1550-4794, 08/2008, pp. 182 - 189
Silicon nanophotonics holds the promise of revolutionizing computing by enabling parallel architectures that combine unprecedented performance and ease of use... 
Magnetic cores | Modulation | Bandwidth | Waveguide lasers | Detectors | Silicon | Optical waveguides
Conference Proceeding
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