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Proceedings of the 2016 ACM SIGMETRICS International Conference on measurement and modeling of computer science, 06/2016, pp. 351 - 363
Modern memory access schedulers employed in GPUs typically optimize for memory throughput. They implicitly assume that all requests from different cores are... 
criticality | memory system | latency tolerance | gpus
Conference Proceeding
2015 International Conference on Parallel Architecture and Compilation (PACT), ISSN 1089-795X, 10/2015, pp. 25 - 38
In a GPU, all threads within a warp execute the same instruction in lockstep. For a memory instruction, this can lead to memory divergence: the memory requests... 
Multithreading | Instruction sets | Memory management | Memory divergence | Graphics processing units | Delays | Parallel architectures | GPU | Resource Management | Warp | Utilities | Divergence | Architecture | Stall | Queues | Medic | Delay
Conference Proceeding
Proceedings of the 40th Annual International Symposium on computer architecture, ISSN 1063-6897, 06/2013, pp. 332 - 343
In this paper, we present techniques that coordinate the thread scheduling and prefetching decisions in a General Purpose Graphics Processing Unit (GPGPU)... 
GPGPUs | latency tolerance | prefetching | warp scheduling | Latency Tolerance | Prefetching | Warp Scheduling
Conference Proceeding
Proceedings of the 22nd international conference on parallel architectures and compilation techniques, ISSN 1089-795X, 10/2013, pp. 157 - 166
General-purpose graphics processing units (GPGPUs) are at their best in accelerating computation by exploiting abundant thread-level parallelism (TLP) offered... 
GPGPUs | scheduling | thread-level parallelism | Measurement | Instruction sets | Pipelines | Graphics processing units | Transform coding | Parallel processing | Kernel
Conference Proceeding
Proceedings of the 2016 International Conference on parallel architectures and compilation, ISSN 1089-795X, 09/2016, pp. 31 - 44
Processing data in or near memory (PIM), as opposed to in conventional computational units in a processor, can greatly alleviate the performance and energy... 
near data computing | kernel scheduling | processing-in-memory | gpu | Predictive models | Memory management | Kernel | Graphics processing units | Random access memory | Bandwidth | GPU
Conference Proceeding
ACM SIGMETRICS Performance Evaluation Review, ISSN 0163-5999, 06/2016, Volume 44, Issue 1, pp. 351 - 363
Journal Article
Proceedings of the 47th Annual IEEE/ACM International Symposium on microarchitecture, ISSN 1072-4451, 12/2014, Volume 2015-, Issue January, pp. 114 - 126
Heterogeneous architectures consisting of general-purpose CPUs and throughput-optimized GPUs are projected to be the dominant computing platforms for many... 
Graphics processing units | GPUs | thread-level parallelism | heterogeneous architectures | CPU-GPU | concurrency | Concurrent computing | System performance | Computer architecture | Bandwidth | scheduling | Central Processing Unit | Resource management | resource management | GPUS
Conference Proceeding
2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), ISSN 1530-0897, 02/2018, Volume 2018-, pp. 247 - 258
Managing the thread-level parallelism (TLP) of GPGPU applications by limiting it to a certain degree is known to be effective in improving the overall... 
Measurement | Graphics processing units | Random access memory | GPUs | Bandwidth | Interference | Bandwidth Management | Throughput | Indexes | Fairness
Conference Proceeding
Proceedings of the 2016 International Conference on parallel architectures and compilation, ISSN 1089-795X, 09/2016, pp. 17 - 30
To improve the performance of Graphics Processing Units (GPUs) beyond simply increasing core count, architects are recently adopting a scale-up approach: the... 
Power demand | Registers | Pipelines | Memory management | Graphics processing units | Queueing analysis
Conference Proceeding
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), ISSN 1072-4451, 10/2016, Volume 2016-, pp. 1 - 13
As we integrate data-parallel GPUs with general-purpose CPUs on a single chip, the enormous cache traffic generated by GPUs will not only exhaust the limited... 
Multicore processing | Nonvolatile memory | System-on-chip | Central Processing Unit | Graphics processing units | Random access memory
Conference Proceeding
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), ISSN 1072-4451, 10/2018, Volume 2018-, pp. 908 - 920
The Automata Processor (AP) accelerates applications from domains ranging from machine learning to genomics. However, as a spatial architecture, it is unable... 
Learning automata | Accelerators | Automata | Random access memory | Machine learning | Parallel processing | Routing | Acceleration | Performance
Conference Proceeding
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), ISSN 1530-0897, 02/2017, pp. 649 - 660
Dynamic parallelism (DP) is a promising feature for GPUs, which allows on-demand spawning of kernels on the GPU without any CPU intervention. However, this... 
Performance evaluation | Instruction sets | Graphics processing units | Parallel processing | Benchmark testing | Hardware | Kernel
Conference Proceeding
ACM Transactions on Architecture and Code Optimization (TACO), ISSN 1544-3566, 10/2018, Volume 15, Issue 3, pp. 1 - 23
To exploit parallelism and scalability of multiple GPUs in a system, it is critical to place compute and data together. However, two key techniques that have... 
compiler technique | hybrid data layout | profiling | Multiple GPUs | compute and data localization | Profiling | Data localization | Compiler technique | Hybrid data layout | Compute | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | COMPUTER SCIENCE, THEORY & METHODS
Journal Article
Proceedings of the 44th Annual International Symposium on computer architecture, ISSN 1063-6897, 06/2017, Volume 128643, pp. 678 - 690
High-performance computing, enterprise, and datacenter servers are driving demands for higher total memory capacity as well as memory performance. Memory... 
memory cube | high-performance computing | memory network | nonvolatile memory | Network topology | Memory management | Random access memory | non-volatile memory | Topology | Pins | Servers | Manganese | Memory network | Nonvolatile memory | High-performance computing | Memory cube
Conference Proceeding
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), ISSN 1530-0897, 03/2016, Volume 2016-, pp. 297 - 308
The interconnect or network on chip (NoC) is an increasingly important component in processors. As systems scale up in size and functionality, the ability to... 
Solid modeling | Analytical models | Protocols | Computational modeling | Graphics processing units | Coherence | Central Processing Unit | Networks | Traffic flow | Computer simulation | Architecture | Methodology | Traffic engineering | Central processing units | System on chip
Conference Proceeding
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), ISSN 1530-0897, 02/2017, pp. 85 - 96
The challenges to push computing to exaflop levels are difficult given desired targets for memory capacity, memory bandwidth, power efficiency, reliability,... 
Three-dimensional displays | Architecture | Graphics processing units | Computer architecture | Bandwidth | Supercomputers | Central Processing Unit
Conference Proceeding
2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), ISSN 1530-0897, 02/2018, Volume 2018-, pp. 608 - 619
Modern GPU frameworks use a two-phase compilation approach. Kernels written in a high-level language are initially compiled to an implementation agnostic... 
Graphics processing units | ABI | Registers | GPU | Intermediate Representation | Microarchitecture | Runtime | Simulation | ISA | Computer architecture | Hardware | Kernel | Intermediate Language
Conference Proceeding
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), ISSN 1063-6897, 06/2018, pp. 726 - 738
System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking of an SoC into smaller "chiplets." A chiplet-based SoC design process... 
deadlock-avoidance | chiplet | Government | Graphics processing units | Computer architecture | System recovery | Routing | Silicon | Topology | Deadlock-avoidance | Chiplet
Conference Proceeding
ACM SIGPLAN Notices, ISSN 1523-2867, 04/2013, Volume 48, Issue 4, pp. 395 - 406
Emerging GPGPU architectures, along with programming models like CUDA and OpenCL, offer a cost-effective platform for many applications by providing high... 
GPGPUs | Latency Tolerance | Scheduling | Prefetching | Design | COMPUTER SCIENCE, SOFTWARE ENGINEERING | Performance
Journal Article
Proceedings of the eighteenth international conference on architectural support for programming languages and operating systems, 03/2013, pp. 395 - 406
Emerging GPGPU architectures, along with programming models like CUDA and OpenCL, offer a cost-effective platform for many applications by providing high... 
GPGPUs | scheduling | latency tolerance | prefetching | Gpgpus | Latency tolerance | Scheduling | Prefetching
Conference Proceeding
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