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IEICE Transactions on Information and Systems, ISSN 0916-8532, 12/2019, Volume E102.D, Issue 12, pp. 2280 - 2280
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 04/2017, Volume 66, Issue 4, pp. 702 - 716
Journal Article
IEICE Transactions on Information and Systems, ISSN 0916-8532, 2019, Volume E102.D, Issue 2, pp. 247 - 260
Journal Article
IEICE Transactions on Information and Systems, ISSN 0916-8532, 2018, Volume E101.D, Issue 12, pp. 2922 - 2932
Journal Article
IEICE Transactions on Information and Systems, ISSN 0916-8532, 2018, Volume E101.D, Issue 9, pp. 2258 - 2268
In parallel processing applications, a few worker nodes called “stragglers”, which execute their tasks significantly slower than other tasks, increase the... 
FPGA | straggler | MapReduce | Straggler | Parallel processing | Computer simulation | Computation | Field programmable gate arrays | Nodes | Ethernet
Journal Article
IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, 02/2019, Volume 30, Issue 2, pp. 315 - 330
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 03/2014, Volume 63, Issue 3, pp. 748 - 763
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 02/2016, Volume 24, Issue 2, pp. 493 - 506
Journal Article
IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, 04/2017, Volume 28, Issue 4, pp. 989 - 1001
Journal Article
IEICE - Transactions on Information and Systems, ISSN 0916-8532, 01/2016, Volume E99.D, Issue 11, pp. 2694 - 2704
A number of parallel applications run on a high-performance computing (HPC) system simultaneously. Job mapping and scheduling become crucial to improve system... 
Networks | Data centers | Algorithms | Utilization | Supercomputers | Scheduling | Mapping
Journal Article
IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, 07/2015, Volume 26, Issue 7, pp. 2051 - 2060
Random network topologies have been proposed to create low-diameter, low-latency interconnection networks in large-scale computing systems. However, these... 
Routing | Network topology | Topology | Optical switches | Layout | Ports (Computers) | cabinet layout | interconnection networks | Network topologies | high-performance computing | TOPOLOGIES | PERFORMANCE | HYPERCUBE | NETWORKS | COMPUTER SCIENCE, THEORY & METHODS | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEICE Transactions on Information and Systems, ISSN 0916-8532, 2017, Volume E100.D, Issue 12, pp. 2796 - 2807
End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported... 
network topology | interconnection networks | high performance computing | High performance computing | Interconnection networks | Network topology | COMPUTER SCIENCE, SOFTWARE ENGINEERING | COMPUTER SCIENCE, INFORMATION SYSTEMS | TOPOLOGIES | Hops | Tables | Switching theory | Routing (telecommunications) | Tables (data)
Journal Article
IEICE - Transactions on Information and Systems, ISSN 0916-8532, 05/2015, Volume E98.D, Issue 3, pp. 661 - 670
Recently network bandwidth becomes a performance concern particularly for collective communication since bisection bandwidths of supercomputers become far less... 
Networks | Simulation | Coding | Interconnection | Bandwidth | Supercomputers | Counting | Quantitative analysis
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 04/2011, Volume 30, Issue 4, pp. 520 - 533
Journal Article
IEICE - Transactions on Information and Systems, ISSN 0916-8532, 11/2016, Volume E99.D, Issue 12, pp. 2871 - 2880
The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with... 
Design engineering | Chips (electronics) | Stacking | Chips | Staking | Inductive coupling | System on chip | Routing (telecommunications)
Journal Article
IEICE Transactions on Information and Systems, ISSN 0916-8532, 2017, Volume E100.D, Issue 8, pp. 1798 - 1806
Inter-switch networks for HPC systems and data-centers can be improved by applying random shortcut topologies with a reduced number of hops. With minimal... 
time complexity | deadlock-free routing | high performance computing | High performance computing | Time complexity | Deadlock-free routing | COMPUTER SCIENCE, SOFTWARE ENGINEERING | SMALL-WORLD | COMPUTER SCIENCE, INFORMATION SYSTEMS | NETWORKS | Algorithms | Heuristic methods | Virtual networks | Hops | Switching theory | Hash based algorithms | Complexity
Journal Article
2017 IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS), ISSN 1521-9097, 12/2017, Volume 2017-, pp. 664 - 673
Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve... 
Deadlock free Routing Algorithm | Irregular Networks | Adaptation models | Network topology | High Performance Computing | Two dimensional displays | Switches | Virtual Channels | System recovery | Routing | Topology | Interconnection Networks
Conference Proceeding
IEICE - Transactions on Information and Systems, ISSN 0916-8532, 11/2015, Volume E99.D, Issue 5, pp. 1275 - 1284
System expandability becomes a major concern for highly parallel computers and data centers, because their number of nodes gradually increases year by year. In... 
Networks | Power consumption | Interconnection | Parallel computers | Shortest-path problems | Cabinets | Topology | Cables
Journal Article
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