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IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 10/2014, Volume 22, Issue 10, pp. 2054 - 2066
Journal Article
IEEE Transactions on Circuits and Systems II: Express Briefs, ISSN 1549-7747, 11/2014, Volume 61, Issue 11, pp. 895 - 899
Journal Article
IEEE Journal on Selected Areas in Communications, ISSN 0733-8716, 01/2014, Volume 32, Issue 1, pp. 88 - 101
Journal Article
IEEE Transactions on Circuits and Systems II: Express Briefs, ISSN 1549-7747, 08/2015, Volume 62, Issue 8, pp. 786 - 790
Journal Article
IEEE Journal on Selected Areas in Communications, ISSN 0733-8716, 05/2019, Volume 37, Issue 5, pp. 1072 - 1084
The most demanding tenants of shared clouds require complete isolation from their neighbors, in order to guarantee that their application performance is not... 
software defined networking | computer network management | Communication networks | computer networks | MANAGEMENT | NETWORKS | TELECOMMUNICATIONS | ENGINEERING, ELECTRICAL & ELECTRONIC | Links | Tenants | Graph theory | Servers (computers) | Provisioning
Journal Article
IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 01/2013, Volume 60, Issue 1, pp. 211 - 221
Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers... 
Resistance | Adaptation models | Computational modeling | Memristors | memristor | Memristive systems | SPICE | window function | Semiconductor process modeling | Mathematical model | Integrated circuit modeling | ENGINEERING, ELECTRICAL & ELECTRONIC | Usage | Logic circuitry | Complementary metal oxide semiconductors | Simulation methods | Innovations
Journal Article
2015, 2015, ISBN 9781461408208, 245
This book examines design and migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects, covering scaling-dependent... 
Engineering | Electronic circuit design | Electronic circuits | Processor Architectures | Electronics and Microelectronics, Instrumentation | Circuits and Systems | Integrated circuits | Interconnects (Integrated circuit technology) | Embedded computer systems
eBook
Journal of Systems Architecture, ISSN 1383-7621, 2004, Volume 50, Issue 2, pp. 105 - 128
We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC), and derive related Network on Chip (NoC) architecture and design... 
QoS architecture | Network on chip | QNoC | Wormhole switching | QNoC design process | network on chip | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | wormhole switching | Models | Communication
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 07/2010, Volume 18, Issue 7, pp. 1107 - 1117
An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link... 
Protocols | serial communication | Delay effects | LEDR | Crosstalk | SERDES | Throughput | Synchronization | Communication standards | current signaling | Low voltage | Wires | SPICE | Driver circuits | Clocks | DESIGN | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | OPTIMIZATION | ENGINEERING, ELECTRICAL & ELECTRONIC | Communication | Drivers | Circuits | High speed | Swing | Very large scale integration | Links | Serials | Wire
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 10/2010, Volume 29, Issue 10, pp. 1650 - 1654
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 09/2015, Volume 23, Issue 9, pp. 1750 - 1759
In recent years, memristive technologies, such as resistive random access memory (RRAM), have emerged. These technologies are usually considered as alternates... 
Resistance | memristive device | Pipelines | Memristors | Metals | Random access memory | memristor | multithreading | Registers | CMOS integrated circuits | resistive random access memory (RRAM) | Flip flop | CIRCUITS | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | MODEL | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
2011 IEEE 29th International Conference on Computer Design (ICCD), ISSN 1063-6404, 10/2011, pp. 142 - 147
Memristors can be used as logic gates. No design methodology exists, however, for memristor-based combinatorial logic. In this paper, the design and behavior... 
Resistance | design methodology | IMPLY | Computational modeling | Memristors | Switches | memristor | Logic gates | Threshold voltage | logic | memristive systems | Integrated circuit modeling
Conference Proceeding
Microprocessors and Microsystems, ISSN 0141-9331, 11/2014, Volume 38, Issue 8, pp. 814 - 825
Hierarchical topologies are frequently proposed for large Networks-on-Chip (NoCs). Hierarchical architectures utilize, at the upper levels, long links of the... 
Repeaters | NoCs | In-chip interconnect | Wire sizing | Hierarchical NoCs | Network-on-Chip | INSERTION | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ON-CHIP | MODEL | ENGINEERING, ELECTRICAL & ELECTRONIC | OPTIMIZATION | COMPUTER SCIENCE, THEORY & METHODS | ELMORE DELAY | Costs | Architecture | Insertion | Links | Proposals | Sizing | Delay
Journal Article
IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, 09/2015, Volume 26, Issue 9, pp. 2479 - 2492
Journal Article
Microprocessors and Microsystems, ISSN 0141-9331, 02/2016, Volume 40, pp. 154 - 166
As the number of modules grows, performance scalability of planar topology Networks-on-Chip (NoCs) becomes limited due to increasing hop-distances, since long... 
Adaptive routing | Low latency design | Load balancing | Traffic monitoring | Hierarchical networks on chip | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | CHIP | COMPUTER SCIENCE, THEORY & METHODS | ENGINEERING, ELECTRICAL & ELECTRONIC | Design engineering | Networks | Traffic flow | Dynamics | Traffic engineering | Computer networks | Management | Dynamical systems
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 08/2010, Volume 18, Issue 8, pp. 1262 - 1262
In the above titled paper (ibid., vol. 18, no. 5, pp. 689-696, May 10), the formula and the caption in Fig. 3 appeared incorrectly. The correct figure is... 
Capacitance | Minimization methods | Large-scale systems | Delay effects | Logic | Radio access networks
Journal Article
Journal of Parallel and Distributed Computing, ISSN 0743-7315, 09/2016, Volume 95, pp. 3 - 14
Additional transistors available in each process generation are used to increase the number of cores on chip. This trend results in high execution unit... 
Multicores | Scheduling | Energy efficiency | Energy Friendly Scheduler | Performance monitors | COMPUTER SCIENCE, THEORY & METHODS | Energy conservation | Analysis | Distributed processing | Buses (vehicles) | Operating systems | Dynamics | Bandwidth | Monitors | Mathematical models | Dynamical systems
Journal Article
Integration, the VLSI Journal, ISSN 0167-9260, 2009, Volume 42, Issue 2, pp. 103 - 115
An asynchronous router for quality-of-service Networks on Chip (QNoC) is presented. It combines multiple service levels (SL) with multiple equal-priority... 
Virtual channels | NoC | Arbitration | Quality of service | Asynchronous circuits | NETWORK | DESIGN | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC | SYNCHRONIZATION | CHIP | ARCHITECTURE | LATENCY | Bridge/routers | Very-large-scale integration | Venture capital companies
Journal Article
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