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routing (22) 22
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analysis (3) 3
apparatus or arrangements employing analogous techniques usingwaves other than optical waves (3) 3
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IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 08/2008, Volume 55, Issue 7, pp. 1911 - 1920
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 04/2012, Volume 31, Issue 4, pp. 644 - 648
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 12/2012, Volume 20, Issue 12, pp. 2184 - 2197
Journal Article
ETRI Journal, ISSN 1225-6463, 06/2011, Volume 33, Issue 3, pp. 374 - 381
Journal Article
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, ISSN 1530-1591, 03/2015, Volume 2015-, pp. 1647 - 1652
This paper presents an integer linear programming approach to transistor placement problem for CMOS standard cells with objectives of minimizing cell width,... 
transistor pairing | transistor folding | transistor placement | standard cell | Wiring | Runtime | Transistor placement | Wires | Layout | Logic gates | Transistors | Standards
Conference Proceeding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 12/2002, Volume 10, Issue 6, pp. 929 - 934
Journal Article
Proceedings of the Conference on design, automation and test in europe, ISSN 1530-1591, 03/2012, pp. 1479 - 1482
This paper presents a simple method for design and analysis of a via-configurable routing fabric formed by an array of routing fabric blocks (RFBs). The method... 
routing | structured ASIC | regular fabric | via configurable | design for manufacturity | Application specific integrated circuits | Measurement | Wires | Layout | Routing | Fabrics | Arrays
Conference Proceeding
Proceedings of the Conference on design, automation and test in europe, ISSN 1530-1591, 03/2010, pp. 514 - 519
Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power... 
structured ASIC | low power | via-configurable | power-gating | Costs | Logic design | Delay | Application specific integrated circuits | Sleep | Voltage | Libraries | Field programmable gate arrays | Logic arrays | Power engineering and energy | Via-configurable | Low power | Structured ASIC | Power-gating
Conference Proceeding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 10/2002, Volume 21, Issue 10, pp. 1209 - 1211
Journal Article
2009 Asian Test Symposium, ISSN 1081-7735, 11/2009, pp. 325 - 330
This paper presents a run-length-based compression method considering dimensions of pattern information. Information such as pattern length and number of... 
Test data compression | Costs | pattern run-length | SOC | Encoding | Decoding | Circuit faults | Circuit testing | ATE | Integrated circuit testing | Intellectual property | Hardware | code-based testing | Huffman coding | Code-based testing | Pattern run-length
Conference Proceeding
Journal of the Chinese Institute of Engineers, ISSN 0253-3839, 03/2010, Volume 33, Issue 2, pp. 263 - 270
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. A simulation_based test vector ordering approach to... 
scan design | transition density | test vector ordering | switching activity | Transition density | Test vector ordering | Switching activity | Scan design | ENGINEERING, MULTIDISCIPLINARY
Journal Article
IEEE Transactions on Automation Science and Engineering, ISSN 1545-5955, 10/2007, Volume 4, Issue 4, pp. 589 - 595
Journal Article
2009 Asian Test Symposium, ISSN 1081-7735, 11/2009, pp. 111 - 116
Large test data volume and excessive testing power are two strict challenges for VLSI testing. This paper presents a deterministic BIST using multiple LFSRs to... 
low-power testing | System testing | Costs | minimum transition fill | test data compression | Built-in self-test | Circuit faults | Circuit testing | Linear feedback shift registers | Automatic testing | Integrated circuit testing | BIST | multiple LFSRs | Hardware | Power generation | Minimum transition fill | Test data compression | Multiple LFSRs | Low-power testing
Conference Proceeding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 04/2012, Volume 31, Issue 4, pp. 644 - 648
This paper presents a new pattern run-length compression method whose decompressor is simple and easy to implement. It encodes 2 | n | runs of compatible or... 
Multiplexing | Test data compression | pattern run-length | Encoding | Automated test equipment (ATE) | Decoding | System-on-a-chip | Synchronization | circuit under test (CUT) | Clocks | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS | test data compression | POWER | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), ISSN 1092-3152, 11/2017, Volume 2017-, pp. 855 - 856
The CAD Contest at ICCAD[1], [2], [3], [4], [5], [6] is a challenging, multi-month R&D competition, focusing on modern and practical problems at the forefront... 
Integrated circuits | ECO | logic synthesis | Design automation | Benchmark testing | Programming | Routing | placement | Standards | Logic synthesis | Placement
Conference Proceeding
Proceedings of the conference on design, automation and test in europe, ISSN 1530-1591, 04/2007, pp. 1212 - 1217
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are... 
Computer science | Design engineering | Costs | Computer aided manufacturing | Wires | Routing | Libraries | Pins | Bipartite graph | Standards development
Conference Proceeding
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 12/2014, pp. 634 - 637
Transition inversion coding (TIC) can reduce serial bus power dissipation by negating the even-numbered bits of a data word if the number of transitions in the... 
Power demand | bus encoding | Microprocessors | Distributed databases | Computer architecture | Very large scale integration | low power | Encoding | Decoding | error detection | serial trasmision
Conference Proceeding
Proceedings of the 35th International Conference on computer-aided design, ISSN 1092-3152, 11/2016, Volume 7-10-, pp. 1 - 2
The CAD Contest at ICCAD is a challenging, multi-month competition, focusing on advanced, real-world problems in the field of Electronic Design Automation... 
logic synthesis | design verification | design for manufacturing | Industries | Integrated circuit synthesis | Design verification | Design automation | Logic synthesis | Pattern classification | Benchmark testing | Design for manufacturing | Manufacturing | Circuit faults
Conference Proceeding
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 10/2016, pp. 534 - 537
As features in semiconductor technology become extremely scaled down, manufacturability is becoming a great challenge. Owing to the delayed adoption of new... 
Detailed Routing | Standard Cell Layout Synthesis | Design automation | Conferences | Lithography | Asia | Multiple Patterning Lithography | Routing | Design for Manufacturing | Standards | Gridless Routing Model
Conference Proceeding
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 11/2015, pp. 910 - 911
The 2015 CAD Contest at ICCAD presents cutting-edge, real-world EDA problems and challenging benchmarks derived from modern industrial designs. It also... 
Computer science | Design automation | Three-dimensional displays | Cooling | Benchmark testing | Cities and towns | Physical design | Design engineering | Conferences | Communities | Electronic design automation | Benchmarks | Design analysis | Computer aided design | Standards
Conference Proceeding
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