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2008, ISBN 9780387309286, 327
Unified Treatment of Data Collection, Modeling, and Statistical CADCovers From Fabrication to Design to CADDeals With the Extraction of Fab Information into... 
Energy Technology & Engineering | Electronic circuit design | Methodology | Statistical methods | Engineering | Circuits and Systems | Computer-Aided Engineering (CAD, CAE) and Design | Electronic and Computer Engineering
eBook
by Bhangu, Aneel and Ademuyiwa, Adesoji O and Aguilera, Maria Lorena and Alexander, Philip and Al-Saqqa, Sara W and Borda-Luque, Giuliano and Costas-Chavarri, Ainhoa and Drake, Thomas M and Ntirenganya, Faustin and Fitzgerald, J Edward and Fergusson, Stuart J and Glasbey, James and Ingabire, JC Allen and Ismaïl, Lawani and Salem, Hosni Khairy and Kojo, Anyomih Theophilus Teddy and Lapitan, Marie Carmela and Lilford, Richard and Mihaljevic, Andre L and Morton, Dion and Mutabazi, Alphonse Zeta and Nepogodiev, Dmitri and Adisa, Adewale O and Ots, Riinu and Pata, Francesco and Pinkney, Thomas and Poškus, Tomas and Qureshi, Ahmad Uzair and Ramos-De la Medina, Antonio and Rayne, Sarah and Shaw, Catherine A and Shu, Sebastian and Spence, Richard and Smart, Neil and Tabiri, Stephen and Harrison, Ewen M and Khatri, Chetan and Mohan, Midhun and Jaffry, Zahra and Altamini, Afnan and Kirby, Andrew and Søreide, Kjetil and Recinos, Gustavo and Cornick, Jen and Modolo, Maria Marta and Iyer, Dushyant and King, Sebastian and Arthur, Tom and Nahar, Sayeda Nazmum and Waterman, Ade and Walsh, Michael and Agarwal, Arnav and Zani, Augusto and Firdouse, Mohammed and Rouse, Tyler and Liu, Qinyang and Correa, Juan Camilo and Talving, Peep and Worku, Mengistu and Arnaud, Alexis and Kalles, Vassilis and Kumar, Basant and Kumar, Sunil and Amandito, Radhian and Quek, Roy and Ansaloni, Luca and Altibi, Ahmed and Venskutonis, Donatas and Zilinskas, Justas and Poskus, Tomas and Whitaker, John and Msosa, Vanessa and Tew, Yong Yong and Farrugia, Alexia and Borg, Elaine and Bentounsi, Zineb and Gala, Tanzeela and Al-Slaibi, Ibrahim and Tahboub, Haya and Alser, Osaid H and Romani, Diego and Shu, Sebestian and Major, Piotr and Mironescu, Aurel and Bratu, Matei and Kourdouli, Amar and Ndajiwo, Aliyu and Altwijri, Abdulaziz and Alsaggaf, Mohammed Ubaid and Gudal, Ahmad and Jubran, Al Faifi and Seisay, Sam and Lieske, Bettina and Ortega, Irene and Jeyakumar, Jenifa and Senanayake, Kithsiri J and Abdulbagi, Omar and Cengiz, Yucel and Raptis, Dmitri and Altinel, Yuksel and ... and GlobalSurg Collaborative
The Lancet Infectious Diseases, ISSN 1473-3099, 05/2018, Volume 18, Issue 5, pp. 516 - 525
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 01/2015, Volume 23, Issue 1, pp. 118 - 130
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 10/2015, Volume 23, Issue 10, pp. 2327 - 2331
In this brief, a temperature- and variation-aware electromigration analysis (T-VEMA) tool for power grid wires is described. First, T-VEMA performs a two-stage... 
Computational modeling | Wires | Electromigration (EM) | Integrated circuit interconnections | process variation | Power grids | Thermal analysis | jL product | Integrated circuit modeling | Current density | thermal analysis | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IET Computers and Digital Techniques, ISSN 1751-8601, 07/2015, Volume 9, Issue 4, pp. 185 - 186
Journal Article
IET Computers & Digital Techniques, ISSN 1751-8601, 07/2015, Volume 9, Issue 4, pp. 185 - 186
Journal Article
IBM Journal of Research and Development, ISSN 0018-8646, 2006, Volume 50, Issue 4-5, pp. 433 - 449
Journal Article
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 03/2019, pp. 1249 - 1252
On-Chip SRAMs are an integral part of safety-critical System-on-Chips. At the same time however, they are also most susceptible to reliability threats such as... 
Degradation | Application-Specific | Random access memory | BTI | Aging Mitigation | Aging | On-Chip SRAM | Threshold voltage | SRAM Design Exploration | Transistors | Reliability | Stress
Conference Proceeding
Proceedings of SPIE - The International Society for Optical Engineering, ISSN 0277-786X, 2012, Volume 8327
Double patterning (DP) in a litho-etch-litho-etch (LELE) process is an attractive technique to scale the K 1 factor below 0.25. For dense bidirectional layers... 
Coloring | Patterning | Methodology | Decomposition | Stitches | Density | Stitching | Complexity
Conference Proceeding
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), ISSN 1530-1591, 03/2010, pp. 1011 - 1016
Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic... 
Circuit topology | Latches | CMOS logic circuits | Random access memory | CMOS technology | Pulse inverters | Circuit noise | Circuit faults | Transistors | Resilience
Conference Proceeding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 08/2005, Volume 24, Issue 8, pp. 1204 - 1224
Journal Article