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test data compression (11) 11
engineering, electrical & electronic (8) 8
circuit testing (7) 7
pattern run-length (7) 7
circuit faults (6) 6
encoding (5) 5
engineering, multidisciplinary (5) 5
power (5) 5
automated test equipment (4) 4
circuit under test (4) 4
costs (4) 4
decoding (4) 4
hardware (4) 4
bist (3) 3
built-in self-test (3) 3
circuits (3) 3
computer science (3) 3
computer science, hardware & architecture (3) 3
data compression (3) 3
delay (3) 3
design for testability (3) 3
information science (3) 3
low power testing (3) 3
soc (3) 3
system-on-a-chip (3) 3
telecommunications (3) 3
ate (2) 2
chains (2) 2
circuit simulation (2) 2
circuits and systems (2) 2
clocks (2) 2
compatibility (2) 2
compression (2) 2
computer architecture (2) 2
computer science, information systems (2) 2
computer-aided engineering and design (2) 2
controllability (2) 2
design engineering (2) 2
dual lfsr (2) 2
electronic and computer engineering (2) 2
electronics (2) 2
engineering (2) 2
integrated circuit testing (2) 2
integrated circuits (2) 2
multiplexing (2) 2
observability (2) 2
power consumption (2) 2
power demand (2) 2
routing (2) 2
switches (2) 2
system performance (2) 2
system testing (2) 2
test vector ordering (2) 2
test-data-compression (2) 2
testing (2) 2
transition density (2) 2
very large scale integration (2) 2
algorithms (1) 1
assembly (1) 1
automatic testing (1) 1
benchmark testing (1) 1
benchmarking (1) 1
benchmarks (1) 1
broadcast testing (1) 1
broadcasting (1) 1
caa (1) 1
capture violation problem (1) 1
channel failure (1) 1
characterization and evaluation of materials (1) 1
circuit noise (1) 1
circuit optimization (1) 1
circuit partitioning (1) 1
circuit synthesis (1) 1
clique (1) 1
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clustering (1) 1
cmos (1) 1
cmos technology (1) 1
code-based testing (1) 1
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communication switching (1) 1
compact (1) 1
compressing (1) 1
compression ratio (1) 1
compression tests (1) 1
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design automation (1) 1
deterministic atpg (1) 1
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Journal of the Chinese Institute of Engineers, ISSN 0253-3839, 03/2010, Volume 33, Issue 2, pp. 263 - 270
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. A simulation_based test vector ordering approach to... 
scan design | transition density | test vector ordering | switching activity | Transition density | Test vector ordering | Switching activity | Scan design | ENGINEERING, MULTIDISCIPLINARY
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 04/2012, Volume 31, Issue 4, pp. 644 - 648
This paper presents a new pattern run-length compression method whose decompressor is simple and easy to implement. It encodes 2 | n | runs of compatible or... 
Multiplexing | Test data compression | pattern run-length | Encoding | Automated test equipment (ATE) | Decoding | System-on-a-chip | Synchronization | circuit under test (CUT) | Clocks | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS | test data compression | POWER | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
ETRI Journal, ISSN 1225-6463, 06/2011, Volume 33, Issue 3, pp. 374 - 381
A simple and effective compression method is proposed for multiple-scan testing. For a given test set, each test pattern is compressed from the view of slices.... 
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 04/2012, Volume 31, Issue 4, pp. 644 - 648
Journal Article
IEICE Transactions on Electronics, ISSN 0916-8524, 2008, Volume E91-C, Issue 5, pp. 798 - 805
In this paper, we present a multiple capture approach to reducing the peak power as well as average power consumption during testing. The basic idea behind is... 
Multiple capture technique | Pattern insertion | Test pattern reordering | Capture violation problem | CIRCUITS | pattern insertion | capture violation problem | test pattern reordering | multiple capture technique | ENGINEERING, ELECTRICAL & ELECTRONIC | Power consumption | Circuits | Testing time | Electronics | Insertion | Benchmarking | Chains | Time measurements
Journal Article
Journal of Electronic Testing, ISSN 0923-8174, 6/2010, Volume 26, Issue 3, pp. 393 - 400
Journal Article
Journal of Information Science and Engineering, ISSN 1016-2364, 07/2019, Volume 35, Issue 4, p. 839
High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power... 
Algorithms | Fault detection | Energy dissipation | Test procedures | Chains | Clustering | Target detection
Journal Article
ETRI Journal, ISSN 1225-6463, 06/2011, Volume 33, Issue 3, pp. 374 - 381
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 03/1999, Volume 7, Issue 1, pp. 116 - 120
We propose a fuzzy-based approach which provides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing... 
Circuit optimization | Costs | Current measurement | Voltage | Packaging | Circuit noise | Circuit faults | Circuit testing | Delay | Clocks | CMOS | Partitioning | Performance | Test | Cost | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | cost | performance | test | partitioning | ENGINEERING, ELECTRICAL & ELECTRONIC | Integrated circuits | Design engineering | Electric circuits | Thresholds | Modules | Very large scale integration
Journal Article
Integration, the VLSI Journal, ISSN 0167-9260, 01/2018, Volume 60, pp. 272 - 276
Growing test data volume and excessive test power consumption are two of the major concerns for the industry when testing large integrated circuits.... 
Low power testing | Dual LFSR | Test data compression | TEST COMPRESSION | SCHEME | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | TEST DATA VOLUME | REDUCTION | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Integration, the VLSI Journal, ISSN 0167-9260, 01/2018, Volume 60, p. 272
Growing test data volume and excessive test power consumption are two of the major concerns for the industry when testing large integrated circuits.... 
Studies | Integrated circuits | Energy consumption | Power consumption | Compression ratio | Seeds | Correlation analysis | Data compression | Compression tests | Cubes
Journal Article
2018 IEEE Conference on Dependable and Secure Computing (DSC), 12/2018, pp. 1 - 7
Large test data volume and excessive test power are two strict challenges for VLSI circuit testing. Built-in self-test (BIST) is recognized as a good solution... 
Computer science | low power testing | Power demand | test data compression | BIST | Built-in self-test | Very large scale integration | Encoding | Decoding | dual LFSR
Conference Proceeding
Journal of Electronic Testing, ISSN 0923-8174, 2/2007, Volume 23, Issue 1, pp. 75 - 84
Journal Article
2012 13th International Workshop on Microprocessor Test and Verification (MTV), ISSN 1550-4093, 12/2012, pp. 24 - 29
The excessive power consumption during testing has been a critical issue for scan-based designs. It gets even worst in the capture mode. This method combines... 
deterministic ATPG | low capture power | testing
Conference Proceeding
2012 13th International Workshop on Microprocessor Test and Verification (MTV), ISSN 1550-4093, 12/2012, pp. 30 - 34
Large test data volume and excessive test power are two strict challenges for VLSI testing. This paper presents a BIST scheme adopting dual-LFSR reseeding... 
low power | LFSR | compression | BIST
Conference Proceeding
Journal of the Chinese Institute of Engineers, ISSN 0253-3839, 02/2015, Volume 38, Issue 2, pp. 169 - 180
This paper presents a hybrid compression method for scan-based testing. Four distinctive compression techniques, i.e. frequency-directed run-length codes... 
OSHC | test data compression | FDR | SOC | ENGINEERING, MULTIDISCIPLINARY | DECOMPRESSION | POWER
Journal Article
2012 13th International Workshop on Microprocessor Test and Verification (MTV), ISSN 1550-4093, 12/2012, pp. 60 - 64
This paper presents a two-way multicasting scan (TMS) architecture for test data compression. TMS records the difference address between neighboring broadcasts... 
compression | multicasting | scan-chain
Conference Proceeding
Journal of the Chinese Institute of Engineers, ISSN 0253-3839, 09/2009, Volume 32, Issue 6, pp. 853 - 860
In Dilated Optical Multistage Interconnection Networks constructed by 2 ×2 photonic switches, each input-to-output connection can be established along one path... 
connections-scheduling | clique partitioning problem | DOMINs | faulty switch | Connections-scheduling | Clique partitioning problem | Domins | Faulty switch | MULTISTAGE INTERCONNECTION NETWORKS | ENGINEERING, MULTIDISCIPLINARY | DIAGNOSING CROSSTALK FAULTS
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 04/2012, Volume 31, Issue 4, p. 644
Journal Article
2010 International Computer Symposium (ICS2010), 12/2010, pp. 562 - 567
This paper presents a pattern run-length compression method. Compression is conducted by encoding 2 |n| runs of compatible or inversely compatible patterns... 
Multiplexing | Test data compression | pattern run-length | automated test equipment (ATE) | Benchmark testing | Encoding | Decoding | System-on-a-chip | circuit under test (CUT) | Pattern run-length | Automated test equipment (ATE) | Circuit under test (CUT)
Conference Proceeding
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