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IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 04/2018, Volume 53, Issue 4, pp. 983 - 994
A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any... 
near-memory processing | Memory management | Neurons | Random access memory | neural networks | Parallel processing | in-memory processing | Binary neural networks | reconfigurable array | System-on-chip | Biological neural networks | ternary neural networks | ENGINEERING, ELECTRICAL & ELECTRONIC | Neural networks | Power consumption
Journal Article
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), ISSN 0195-623X, 05/2018, Volume 2018-, pp. 174 - 179
In image recognition, techniques using a convolutional neural network (CNN) have been extensively studied and are widely used in various applications, such as... 
Training | Embedded System | Embedded systems | Computational modeling | Neurons | Two dimensional displays | FPGA | Ternary Deep Learning | Character recognition | Convolutional neural networks
Conference Proceeding
IEICE Transactions on Information and Systems, ISSN 0916-8532, 05/2019, Volume E102.D, Issue 5, pp. 1003 - 1011
The GUINNESS (GUI based binarized neural network synthesizer) is an open-source tool flow for a binarized deep neural network toward FPGA implementation based... 
COMPUTER SCIENCE, SOFTWARE ENGINEERING | COMPUTER SCIENCE, INFORMATION SYSTEMS | deep learning | pruning | machine learning | FPGA
Journal Article
2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 05/2017, pp. 98 - 105
A pre-trained convolutional deep neural network (CNN) is a feed-forward computation perspective, which is widely used for the embedded systems, requires highly... 
Embedded systems | CNN | Convolution | Deep Neural Network | Two dimensional displays | Neural networks | FPGA | Graphics processing units | Hardware | Field programmable gate arrays | Binarized CNN
Conference Proceeding
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), ISSN 1548-3746, 08/2017, Volume 2017-, pp. 116 - 119
The expanding use of deep learning algorithms causes the demands for accelerating neural network (NN) signal processing. For the NN processing, in-memory... 
Neurons | Artificial neural networks | Computer architecture | Signal processing | System-on-chip | Biological neural networks | Engines
Conference Proceeding
2017 International Conference on Field Programmable Technology (ICFPT), 12/2017, Volume 2018-, pp. 168 - 175
An object detection problem consists of two problems: one is classification of detected object category and the other is localization. Frame object detection... 
Microsoft Windows | Two dimensional displays | Graphics processing units | Detectors | Object detection | Proposals | Field programmable gate arrays
Conference Proceeding
FPGA 2018 - Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 02/2018, Volume 2018-, pp. 31 - 40
Conference Proceeding
06/2018
PROBLEM TO BE SOLVED: To provide a neural network circuit device, a neural network, a neural network processing method and a neural network executing program... 
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS | COMPUTING | COUNTING | PHYSICS | CALCULATING
Patent
06/2018
[Problem] To provide a neural network circuit device that does not require a batch normalization circuit, a neural network, a neural network processing method,... 
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS | COMPUTING | COUNTING | PHYSICS | CALCULATING
Patent
2016 International Conference on Field-Programmable Technology (FPT), 12/2016, pp. 277 - 280
A pre-trained deep convolutional neural network (CNN) is a feed-forward computation perspective, which is widely used for the embedded systems, requires high... 
Convolution | Two dimensional displays | Memory management | Neural networks | Table lookup | System-on-chip | Field programmable gate arrays
Conference Proceeding
2017 Symposium on VLSI Circuits, 06/2017, pp. C24 - C25
A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing... 
Neurons | Random access memory | Computer architecture | Artificial neural networks | Very large scale integration | Biological neural networks | Field programmable gate arrays
Conference Proceeding
The Japanese Journal of Antibiotics, ISSN 0368-2781, 1969, Volume 22, Issue 1, pp. 103 - 107
Journal Article
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