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1998, 2nd ed., ISBN 0123229804, xviii, 229
Book
Wireless Personal Communications, ISSN 0929-6212, 11/2019, Volume 109, Issue 2, pp. 823 - 847
Technology scaling facilitates to meet ever increasing demands for a portable and battery operated systems, at the same time causes diminution of length of the... 
Engineering | Signal,Image and Speech Processing | Low leakage | Communications Engineering, Networks | Array structure | Computer Communication Networks | SRAM | Sense amplifier | Cache | Static random access memory | Integrated circuit fabrication | Design and construction | Circuit design | Methods
Journal Article
IEEE/ACM Transactions on Networking, ISSN 1063-6692, 08/2015, Volume 23, Issue 4, pp. 1029 - 1040
Replicating or caching popular content in memories distributed across the network is a technique to reduce peak network loads. Conventionally, the main... 
content distribution | coded caching | Cache memory | Multicast communication | Approximation algorithms | Encoding | Servers | Approximation methods | Cache networks | prefetching | IEEE transactions | DEMAND | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | COMPUTER SCIENCE, THEORY & METHODS | TELECOMMUNICATIONS | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
2017, ISBN 3319487035, Volume 2, 211
This book describes the technology of charge-trapping non-volatile memories and their uses. The authors explain the device physics of each device architecture... 
Electronics and Microelectronics, Instrumentation | Materials Engineering | Materials Science | Memory Structures | Electronic Circuits and Devices | Nanotechnology | Nonvolatile random-access memory
eBook
IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, 01/2017, Volume 28, Issue 1, pp. 72 - 86
Memory access efficiency is a key factor in fully utilizing the computational power of graphics processing units (GPUs). However, many details of the GPU... 
CUDA | Instruction sets | cache structure | Graphics processing units | Computer architecture | Benchmark testing | Throughput | memory hierarchy | Hardware | Kernel | GPU | throughput | PERFORMANCE | COMPUTER SCIENCE, THEORY & METHODS | CACHE | ENGINEERING, ELECTRICAL & ELECTRONIC | Usage | Graphics coprocessors | Mathematical optimization | Analysis | Benchmarks | Hierarchies | Memory (computers)
Journal Article
IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, 01/2016, Volume 27, Issue 1, pp. 66 - 77
Journal Article
by Kim, YK and Moon, B and Kim, DS and Jang, YJ
IEICE ELECTRONICS EXPRESS, ISSN 1349-2543, 08/2019, Volume 16, Issue 16, p. 20190393
A promising solution for assuring ultra-low latency in data-intensive application processing systems is processing in memory (PIM). Although most studies that... 
processing in memory | cache architecture | near-data processing | PIM | data-centric computing | cache management | ENGINEERING, ELECTRICAL & ELECTRONIC | Power consumption | Policies | Computer simulation | Computation | Memory management | Computer architecture | Powder injection molding
Journal Article
11/2013
Moore's Law has helped Field Programmable Gate Arrays (FPGAs) scale continuously in speed, capacity and energy efficiency, allowing the integration of... 
Zipf's Law | Cache Churn Rate | Quality-of-Service | Bandwidth Guarantee | FPGA | Switch Fabric | Memory System | Online Video | Crosspoint Queued Switch | 0544 | XML | Muti-port Memory Controller | Flash
Dissertation
ACM Computing Surveys (CSUR), ISSN 0360-0300, 02/2017, Volume 49, Issue 4, pp. 1 - 38
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 06/2013, Volume 21, Issue 6, pp. 1094 - 1102
Journal Article
Proceedings of the 47th Annual IEEE/ACM International Symposium on microarchitecture, ISSN 1072-4451, 12/2014, Volume 2015-, Issue January, pp. 1 - 12
This paper analyzes the trade-offs in architecting stacked DRAM either as part of main memory or as a hardware-managed cache. Using stacked DRAM as part of... 
stacked DRAM | cache | memory | Memory management | Random access memory | Bandwidth | Organizations | Benchmark testing | Hardware | Software
Conference Proceeding
IEEE Transactions on Information Theory, ISSN 0018-9448, 10/2019, Volume 65, Issue 10, pp. 6146 - 6159
A common way to protect data stored in DRAM and related memory systems is through the use of an error-correcting code such as the extended Hamming code.... 
random access memory | Hamming distance | Source coding | Redundancy | Probabilistic logic | Parity check codes | Error correction codes | Decoding | DESIGN | CODES | COMPUTER SCIENCE, INFORMATION SYSTEMS | CACHE | ERROR PROTECTION | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
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