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IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 01/2007, Volume 42, Issue 1, pp. 17 - 24
This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm(2) die has 1.328-B transistors. Each core has... 
65-nm process technology | Circuit design | Computer architecture | Leakage reduction | Clock distribution | Microprocessor | Shared on-die cache | Voltage domains | microprocessor | computer architecture | leakage reduction | circuit design | voltage domains | clock distribution | shared on-die cache | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 08/2013, Volume 48, Issue 8, pp. 1954 - 1962
An energy efficient on-die 20-way set associative L3 cache of size 20 MB for the Intel ® Xeon ® processor E5 family is presented. It is manufactured in the... 
Access control | redundancy design | Circuit design | power reduction | Redundancy | Random access memory | Metals | Maintenance engineering | on-die cache | clock | SRAM | low Vccmin | Arrays | Clocks | On-die cache | Low Vccmin | Power reduction | Redundancy design | Clock | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 11/2003, Volume 38, Issue 11, pp. 1887 - 1895
This 130-nm Itanium 2 processor implements the explicitly parallel instruction computing (EPIC) architecture and features an on-die 6-MB 24-way set-associative... 
On-die cache | Circuit design | Test | Computer architecture | Power reduction | Clock deskew | Manufacturability | Clock distribution | Microprocessor | Package | Reliability | microprocessor | clock deskew | package | power reduction | test | computer architecture | reliability | on-die cache | circuit design | manufacturability | clock distribution | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 04/2007, Volume 42, Issue 4, pp. 846 - 852
Journal Article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, ISSN 0018-9200, 10/2017, Volume 52, Issue 10, pp. 2589 - 2600
Reducing the operating voltage of digital systems improves energy efficiency, and the minimum operating voltage of a system (V-min) is commonly limited by SRAM... 
reprogrammable redundancy (RR) | Bit bypass (BB) | line disable (LD) | DIE L3 CACHE | V-min | dynamic column redundancy (DCR) | error-correcting codes (ECC) | redundancy | SRAM | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Communications in Computer and Information Science, ISSN 1865-0929, 2016, Volume 592, pp. 3 - 12
Conference Proceeding
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 01/2007, Volume 42, Issue 1, pp. 17 - 25
This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm 2 die has 1.328-B transistors. Each core has two... 
microprocessor | Circuit design | leakage reduction | 65-nm process technology | Microprocessors | Voltage | Computer architecture | Frequency | Transistors | Logic | Subthreshold current | voltage domains | Clocks | clock distribution | shared on-die cache
Journal Article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, ISSN 0018-9200, 01/2005, Volume 40, Issue 1, pp. 195 - 203
The 18-way set-associative, single-ported 9 MB cache for the Itanium((R)) 2 Processor uses 210 identical 48-kB sub-arrays with a 2.21(.)mum(2) cell in a 130-nm... 
microprocessor | power reduction | test | computer architecture | reliability | on-die cache | circuit design | manufacturability | tag array | clock distribution | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 01/2005, Volume 40, Issue 1, pp. 195 - 203
The 18-way set-associative, single-ported 9 MB cache for the Itanium 2 processor uses 210 identical 48-kB sub-arrays with a 2.21-/spl mu/m/sup 2/ cell in a... 
microprocessor | Circuit design | power reduction | test | reliability | on-die cache | Decoding | Delay | tag array | Microprocessors | Computer architecture | Implants | Frequency | Circuit synthesis | Circuit stability | manufacturability | Clocks | Testing | clock distribution
Journal Article
Proceedings of the Second International Symposium on memory systems, 10/2016, Volume 3-06-, pp. 191 - 203
Die-stacked DRAM technology enables a large Last Level Cache (LLC) that provides high bandwidth data access to the processor. However, it requires a large tag... 
last-level cache | Die-stacked DRAM | replacement policy | Last-level cache | Replacement policy
Conference Proceeding
Proceedings of the 42nd Annual IEEE/ACM International Symposium on microarchitecture, ISSN 1072-4451, 12/2009, pp. 222 - 231
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular... 
NUCA | DRAM | 3D die stacking | process variation | Process design | Multicore processing | Stacking | Circuits | Random access memory | Process Variation | 3D Die Stacking | Delay | Space technology | Wires | Permission | Nanoscale devices | Process variation
Conference Proceeding
Proceedings of the 40th Annual International Symposium on computer architecture, ISSN 1063-6897, 06/2013, pp. 416 - 427
Die-stacked DRAM can provide large amounts of in-package, high-bandwidth cache storage. For server and high-performance computing markets, however, such DRAM... 
cache | error protection | die stacking | reliability | Die stacking | Reliability | Cache | Error protection
Conference Proceeding
ACM Transactions on Design Automation of Electronic Systems (TODAES), ISSN 1084-4309, 10/2013, Volume 18, Issue 4, pp. 1 - 23
As technology moves towards finer process geometries, it is becoming extremely difficult to control critical physical parameters such as channel length, gate... 
instruction cache | address translation | Process variation | encoding | Encoding | Instruction cache | Address translation | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | YIELD | CACHE | DIE-TO-DIE | COMPUTER SCIENCE, SOFTWARE ENGINEERING | Algorithms | FREQUENCY | Performance | ADAPTIVE BODY BIAS | DELAY | PARAMETER FLUCTUATIONS | Automation
Journal Article
Proceedings of the 40th annual Design Automation Conference, 06/2003, pp. 706 - 709
This 130nm Itanium® 2 processor implements the Explicitly Parallel Instruction Computing (EPIC) architecture and features an on-die 6MB, 24-way set associative... 
design methodology | on-die cache | test | processor | reliability | Concurrent computing | Computer aided instruction | Design methodology | Integrated circuit interconnections | Computer architecture | Packaging | Dielectrics | Circuit synthesis | Design for manufacture | Copper
Conference Proceeding
Book Chapter
Proceedings of the 44th Annual International Symposium on computer architecture, ISSN 1063-6897, 06/2017, Volume 128643, pp. 469 - 480
With increasing deployment of virtual machines for cloud services and server applications, memory address translation overheads in virtualized environments... 
Address Translation | Very Large TLB | Die-Stacked DRAM | Virtualization | Program processors | Two dimensional displays | Random access memory | Organizations | Benchmark testing | Virtual machining
Conference Proceeding
Proceedings of the 47th Annual IEEE/ACM International Symposium on microarchitecture, ISSN 1072-4451, 12/2014, Volume 2015-, Issue January, pp. 13 - 24
Recent technology advancements allow for the integration of large memory structures on-die or as a die-stacked DRAM. Such structures provide higher bandwidth... 
Die-Stacking | Heterogeneous Memory | Hardware Management | Stacked DRAM | Radiation detectors | Motion segmentation | Memory management | Random access memory | Hardware | Resource management
Conference Proceeding
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