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by Kim, HM and Kwon, DW and Kim, S and Lee, K and Lee, J and Park, E and Lee, R and Kim, H and Park, BG
JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, ISSN 1533-4880, 09/2018, Volume 18, Issue 9, pp. 5882 - 5886
Journal Article
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), ISSN 1530-0897, 02/2014, pp. 356 - 367
Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR (double data rate) DRAM refreshes cells at the rank level. This... 
Out of order | Schedules | DRAM chips | System performance | Standards | Organizations | Computer Science - Hardware Architecture
Conference Proceeding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 5/2019, pp. 1 - 1
This retrospective paper describes the RowHammer problem in Dynamic Random Access Memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014... 
Errors | Memory Systems | Memory management | Failure analysis | DRAM chips | Hardware | DRAM | Vulnerability | Security | Reliability | Technology Scaling
Journal Article
International journal of circuit theory and applications, ISSN 0098-9886, 2018, Volume 46, Issue 7, pp. 1416 - 1425
Summary This study presents a novel approach which enhances the data retention capability of PMOS gain cell based embedded DRAM. The proposed circuit technique... 
DRAM chips | CMOS memory circuits | embedded memory | logic‐compatible DRAM | logic-compatible DRAM | REFRESH | CELL-EMBEDDED DRAM | DYNAMIC MEMORY | 3T GAIN-CELL | ENGINEERING, ELECTRICAL & ELECTRONIC | Retention | CMOS | Immunity
Journal Article
IEEE computer architecture letters, ISSN 1556-6056, 2015, Volume 14, Issue 2, pp. 127 - 131
Bitwise operations are an important component of modern day programming, and are used in a variety of applications such as databases. In this work, we propose... 
Program processors | Capacitors | Random access memory | Computer architecture | Throughput | DRAM | Decoding | DRAM memory | bitwise AND/OR | performance | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Journal Article
ACM Transactions on Design Automation of Electronic Systems (TODAES), ISSN 1084-4309, 07/2019, Volume 24, Issue 4, pp. 1 - 25
As dynamic random access memory (DRAM) cells continue to be scaled down for higher density and capacity, they have more faults. Thus, DRAM reliability becomes... 
DRAM fault recovery | COMPUTER SCIENCE, SOFTWARE ENGINEERING | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | DRAM
Journal Article
Applied physics letters, ISSN 1077-3118, 2009, Volume 95, Issue 4, pp. 043108 - 043108-3
The electrical switching behavior of GeTe-based phase change memory devices is characterized by time resolved experiments. SET pulses with a duration of less... 
switching | LASER-INDUCED CRYSTALLIZATION | PHYSICS, APPLIED | DATA-STORAGE | FILMS | nanotechnology | DRAM chips | germanium compounds | phase change memories
Journal Article
IEEE computer architecture letters, ISSN 1556-6056, 2016, Volume 15, Issue 1, pp. 45 - 49
Journal Article
Journal of Nanoscience and Nanotechnology, ISSN 1533-4880, 2017, Volume 17, Issue 5, pp. 2906 - 2911
Journal Article
Nature (London), ISSN 1476-4687, 2007, Volume 445, Issue 7126, pp. 414 - 417
The primary metric for gauging progress in the various semiconductor integrated circuit technologies is the spacing, or pitch, between the most closely spaced... 
Computer science | Computer memory | Molecular biology | Circuits
Journal Article
MICROMACHINES, ISSN 2072-666X, 02/2019, Volume 10, Issue 2, p. 124
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations.... 
INSTRUMENTS & INSTRUMENTATION | 3D-stacked | low-power | low-latency | NANOSCIENCE & NANOTECHNOLOGY | DRAM | in-DRAM cache
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 12/2017, Volume 64, Issue 12, pp. 4904 - 4909
2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power... 
scaling | silicon on insulator (SOI) and Z | FET | fully depleted (FD) | integration | low power | DRAM | capacitor less | 1T-dynamic random access memory (DRAM) | embedded | Engineering Sciences | Micro and nanotechnologies | Microelectronics
Journal Article
Proceedings of the ACM on Measurement and Analysis of Computing Systems, ISSN 2476-1249, 06/2017, Volume 1, Issue 1, pp. 1 - 42
The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to... 
dram characterization | voltage reduction | performance | memory systems | dram | memory latency | reliability | energy
Journal Article
Nanotechnology, ISSN 0957-4484, 10/2017, Volume 28, Issue 44, p. 445203
The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin... 
retention time | DRAM | sense margin | PHYSICS, APPLIED | PERFORMANCE | MATERIALS SCIENCE, MULTIDISCIPLINARY | NANOSCIENCE & NANOTECHNOLOGY | GATE | TIME | FIELD-EFFECT TRANSISTORS | IMPACT | OPERATION | PROGRESS | CAPACITORLESS 1T-DRAM | DEVICES
Journal Article
Solid State Electronics, ISSN 0038-1101, 01/2015, Volume 103, pp. 7 - 14
•A2RAM devices have been fabricated on 2.5μm and 22nm technologies.•The fabrication is compatible with the CMOS process.•The electrical characteristics show... 
FB-1T-DRAM | DRAM | A2RAM | Silicon-on-insulator | Capacitorless DRAM | Floating-body cell | Memory (Computers) | Complementary metal oxide semiconductors | Prototypes | Memory (computers) | Disturbances | Durability | Endurance | Devices | Immunity | Channels | Engineering Sciences | Micro and nanotechnologies | Microelectronics
Journal Article
Journal Article