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Journal Article
Journal of Experimental Biology, ISSN 0022-0949, 07/2018, Volume 221, Issue 13, pp. jeb183897 - jeb183897
Journal Article
2018 New Generation of CAS (NGCAS), 11/2018, pp. 146 - 149
Dual-rail logic circuits have been used as an effective countermeasure towards a more secure circuit design. However, with technology scaling and lowering of V... 
Latches
Conference Proceeding
IEEE Transactions on Nanotechnology, ISSN 1536-125X, 03/2016, Volume 15, Issue 2, pp. 129 - 136
In this paper, we analyze the effects of aging mechanisms on the soft error susceptibility of both standard and robust latches. Particularly, we consider bias... 
Degradation | MOSFET | Soft Error | Latches | Robust Latch | Aging | Static Latch | Robustness | Threshold voltage | Standards | HIGH-PERFORMANCE | TOLERANT LATCH | PHYSICS, APPLIED | soft error | MATERIALS SCIENCE, MULTIDISCIPLINARY | NANOSCIENCE & NANOTECHNOLOGY | robust latch | SOFT | DESIGNS | ENGINEERING, ELECTRICAL & ELECTRONIC | LOW-COST | aging | Static latch | Designers
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 10/2015, Volume 50, Issue 10, pp. 2319 - 2330
A 7 bit 2 GS/s flash ADC fabricated in a 65nm CMOS process is presented. The proposed cascaded latch interpolation technique achieves a 4 × interpolation... 
Interpolation | Latches | Accuracy | Cascaded latch interpolation | latch interpolation | flash ADC | Ash | clock timing adjustment | Delays | interpolation ADC | Clocks | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 07/2018, Volume 53, Issue 7, pp. 1902 - 1912
A latch-type comparator with a dynamic bias pre-amplifier is implemented in a 65-nm CMOS process. The dynamic bias with a tail capacitor is simple to implement... 
Energy consumption | Latches | Strongarm | Capacitors | charge steering | SAR | Analog-to-digital converter (ADC) | Discharges (electric) | comparator | double-tail latch-type comparator | dynamic biasing | noise | Threshold voltage | latch | Transistors | Signal to noise ratio | SAR ADC | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
2013 IEEE 29th International Conference on Data Engineering (ICDE), ISSN 1063-6382, 04/2013, pp. 302 - 313
The emergence of new hardware and platforms has led to reconsideration of how data management systems are designed. However, certain basic functions such as... 
Latches | Vectors | Hardware | Instruction sets | Indexes | Ash
Conference Proceeding
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 01/2013, Volume 48, Issue 1, pp. 66 - 81
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 06/2011, Volume 46, Issue 6, pp. 1321 - 1336
The power consumption of wireline circuits has become increasingly more critical as the pin count and data rate rise. This paper describes a power scaling... 
decision-feedback equalizers | high-speed equalizers | Latches | Noise | Bit error rate | Decision feedback equalizers | latch sensitivity | CML latch | Sensitivity | unrolled DFE | CMOS integrated circuits | Clocks | latch offset | TRANSCEIVER | CLOCK | ENGINEERING, ELECTRICAL & ELECTRONIC | Drawing | Design engineering | CMOS | Equalizers | Power consumption | Circuits | Tradeoffs | Counting
Journal Article
2012 39th Annual International Symposium on Computer Architecture (ISCA), ISSN 1063-6897, 06/2012, pp. 368 - 379
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served... 
Parallel processing | Latches | Tiles | Random access memory | Delay | Organizations
Conference Proceeding
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 07/2004, Volume 39, Issue 7, pp. 1148 - 1158
Journal Article
Science, ISSN 0036-8075, 07/2015, Volume 349, Issue 6247, pp. 464 - 464
At the Alzheimer's Association International Conference in Washington, D.C., last week, researchers expressed cautious optimism that the field is gaining... 
Proteins | Brain | Latches | Conferences | Meetings | Antibodies
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 06/2012, Volume 47, Issue 6, pp. 1483 - 1496
Many mobile SoC chips employ a "two-macro" approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or... 
Performance evaluation | Latches | Low VDDmin | Random access memory | Switches | nvSRAM | RRAM | Resistance | Nonvolatile memory | Memristors | memristor | memristor latch | nonvolatile SRAM | vertical-stacked | CHIP | NV-SRAM | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Electron Device Letters, ISSN 0741-3106, 02/2015, Volume 36, Issue 2, pp. 186 - 188
A widely tunable variable capacitor using mechanical switching and a reversible latching mechanism was developed. This variable capacitor can increase the... 
Electrodes | Actuators | Latches | Variable capacitor | Switches Reversible latch | RF MEMS | Wide tuning range | Capacitors | Switches | Capacitance | Tuning | switches | wide tuning range | reversible mechanical latch | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 09/2016, Volume 65, Issue 9, pp. 2820 - 2834
This paper presents a set of eight novel configurations for the design of single event soft error (SE) tolerant latches. Each latch uses a three-transistor... 
Feedback loop | static latch | Latches | Soft error | hardened latch | Delays | Circuit faults | Impedance | transient fault | Transient analysis | Clocks | HIGH-PERFORMANCE | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | LOW-COST | DESIGNS | ENGINEERING, ELECTRICAL & ELECTRONIC | Logic circuitry | Logic design | Research | Impedance (Electricity) | Analysis | CMOS | Faults | Computer simulation | Specifications | Circuits | Soft errors | Delay
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 06/2013, Volume 48, Issue 6, pp. 1429 - 1441
A 6-b 4.1-GS/s flash ADC was fabricated using a 90-nm CMOS with a time-domain latch interpolation technique that reduces the number of front-end dynamic... 
Interpolation | high-speed comparator | Latches | time-domain latch interpolation | Noise | Ash | offset calibration | Flash ADC | Calibration | Time-domain analysis | Clocks | CALIBRATION | VOLTAGE | SAR ADC | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Integration, ISSN 0167-9260, 05/2019, Volume 66, pp. 119 - 127
Energy efficiency is considered to be the most critical design parameter for IoT and other ultra low power applications. However, energy efficient circuits... 
Radiation hardening latch | Soft error | Single event upset (SEU) | Energy efficient latches | Transient fault | Radiation hardening | Latches | Design parameters | Circuits | Soft errors | Internet of Things | Immunity | CMOS | Low voltage | Power management | Energy efficiency | Threshold voltage | Energy management
Journal Article
Journal of Infectious Diseases, ISSN 0022-1899, 01/2018, Volume 217, Issue 1, pp. 93 - 102
Journal Article
IEEE Electron Device Letters, ISSN 0741-3106, 04/2015, Volume 36, Issue 4, pp. 405 - 407
Journal Article
IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 02/2019, Volume 66, Issue 2, pp. 616 - 629
This paper proposes a new debiasing method and its application to fuzzy extractors (FEs) for stable and efficient extraction of uniform random binary responses... 
PUF | Latches | multiple-valued logic | Authentication | debiasing | fuzzy extractors | latch PUF | Iron | Stability analysis | Error correction codes | Circuit stability | Decoding | ROBUST | KEYS | PUFS | ENGINEERING, ELECTRICAL & ELECTRONIC | Extractors
Journal Article
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