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Proceedings of the 42nd Annual International Symposium on computer architecture, ISSN 1063-6897, 06/2015, Volume 13-17-, pp. 235 - 246
DRAM cells require periodic refreshing to preserve data. In JEDEC DDRx devices, a refresh operation is performed via an auto-refresh command, which refreshes... 
Nanoscale devices | Weaving | Random access memory | Clocks | Controllers | Memory management | Preserves | Banks | Commands | Architecture (computers) | Standards | Dynamic random access memory
Conference Proceeding
IEEE Micro, ISSN 0272-1732, 05/2019, Volume 39, Issue 3, pp. 103 - 109
Since its invention half a century ago, dynamic random access memory (DRAM) has required dynamic refresh operations that block read accesses to refreshing... 
DRAM chips | Hardware | Error correction | Servers | Memory management | Bandwidth | COMPUTER SCIENCE, SOFTWARE ENGINEERING | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | Blocking | Static random access memory | Random access memory | Dynamic random access memory
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 01/2016, Volume 65, Issue 1, pp. 108 - 121
Ever-growing application data footprints demand faster main memory with larger capacity. DRAM has been the technology choice for main memory due to its low... 
Performance evaluation | Temperature sensors | performance | Computer architecture | DRAM Refresh | Timing | power | SDRAM | Multicore processor | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC | Multiple core processors | Research | Dynamic cell | Dynamic random access memory
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 11/2019, Volume 68, Issue 11, pp. 1584 - 1596
Emerging data analytic workloads such as graph processing, neural network and edge data preprocesing desire efficient memory read operations. Unfortunately,... 
Performance evaluation | DRAM refresh | redundant data storage | Magnetic resonance imaging | Memory management | Random access memory | computer architecture | Bandwidth | main memory | Throughput | Task analysis | software hardware co-design | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 05/2016, Volume 65, Issue 5, pp. 1507 - 1517
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 03/2019, Volume 68, Issue 3, pp. 362 - 374
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 04/2017, Volume 66, Issue 4, pp. 688 - 701
Journal Article
IEEE Computer Architecture Letters, ISSN 1556-6056, 07/2018, Volume 17, Issue 2, pp. 130 - 133
Refresh operations consume growing portions of DRAM power with increasing DRAM capacity. To reduce the power consumption of such refresh operations, this paper... 
DRAM refresh | DRAM energy | Power demand | Microprocessors | Memory management | Random access memory | Transforms | Benchmark testing | value transformation | ENERGY | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | Reduction | Power consumption | Skips
Journal Article
Electronics Letters, ISSN 0013-5194, 2/2018, Volume 54, Issue 3, pp. 142 - 144
Journal Article
The International Journal of High Performance Computing Applications, ISSN 1094-3420, 1/2018, Volume 32, Issue 1, pp. 74 - 88
Journal Article
Microprocessors and Microsystems, ISSN 0141-9331, 03/2017, Volume 49, pp. 95 - 104
Recently, EDRAM cells have gained much attention as a promising alternative to construct on-chip memories. However, due to inherent characteristics of DRAM... 
Refresh | Last-level cache | Performance | Embedded dynamic random access Memory | Energy-efficiency | ENERGY | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | POWER | COMPUTER SCIENCE, THEORY & METHODS | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 01/2019, Volume 68, Issue 1, pp. 83 - 98
Journal Article
IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, 07/2018, Volume 29, Issue 7, pp. 1469 - 1483
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 09/2015, Volume 34, Issue 9, pp. 1455 - 1466
Journal Article
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, ISSN 1530-0889, 06/2015, Volume 2015-, pp. 427 - 437
Multirate refresh techniques exploit the non-uniformity in retention times of DRAM cells to reduce the DRAM refresh overheads. Such techniques rely on accurate... 
Variable Retention Time | Runtime | Avatars | Refresh Rate | Memory Scrubbing | DRAM chips | Dynamic Random Access Memory | Error Correcting Codes | Error correction codes | Reliability | Performance | Testing | Networks | Profiling | Conferences | Memory management | Run time (computers) | Failure | Dynamic random access memory | Impact analysis
Conference Proceeding
IEEE Transactions on Computers, ISSN 0018-9340, 08/2015, Volume 64, Issue 8, pp. 2169 - 2181
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 03/2017, Volume 25, Issue 3, pp. 833 - 843
The 3-D integration allows IC designs to stack DRAM directly on the top of execution units, which greatly reduces DRAM access latency and improves memory... 
3-D-stacked DRAM | Radiation detectors | Random access memory | 3-D ICs | Bandwidth | DRAM refresh operations | Market research | temperature aware refresh (TAR) | Through-silicon vias | high performance | Standards | ENERGY | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
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