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engineering, electrical & electronic (23) 23
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2001, AD-a391 340.
Performance and reliability are major concerns in the design of large disk arrays. Hellerstein et al. pioneered the study of erasure-resilient codes that allow... 
algorithms | erasure-resilient codes | steiner triple systems | simulation | reliability | disk arrays | data storage systems | set theory | raid arrays | coding | combinatorial analysis | computer disks | arrays | microprocessors | combinatorial design
Government Document
Measurement Techniques, ISSN 0543-1972, 8/2004, Volume 47, Issue 8, pp. 842 - 849
Journal Article
Conference Proceeding
2010 3rd International Symposium on Resilient Control Systems, 08/2010, pp. 121 - 126
The DOD community is interested in multicore system-on-a-chip architectures to host Multi-Level Secure (MLS) command and control systems. These systems must be... 
Program processors | Multi-Level Security | Multicore processing | Linux | Microprocessors | Resilient Systems | Multicore Architecture | System-on-a-chip | Kernel | Multi-level security | Resilient systems | Multicore architecture
Conference Proceeding
Proceedings of the International Conference on computer-aided design, ISSN 1092-3152, 11/2010, pp. 177 - 180
Conference Proceeding
Proceedings of the International Conference on computer-aided design, ISSN 1092-3152, 11/2010, pp. 85 - 88
In this tutorial, a 45nm resilient microprocessor core with error-detection and recovery circuits demonstrates the opportunity for improving performance and energy efficiency by mitigating the impact... 
resilient circuits | timing errors | dynamic variations | error recovery | error detection | resilient design | Latches | Microprocessors | Pipelines | Dynamic variations | Throughput | Delay | Clocks | Error detection | Timing errors | Resilient design | Error recovery | Resilient circuits
Conference Proceeding
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 04/2011, Volume 46, Issue 4, pp. 797 - 805
Journal Article
2011 IEEE International Conference on IC Design & Technology, ISSN 2381-3555, 05/2011, pp. 1 - 5
Supply voltage (V CC ) scaling is the most effective technique for reducing the energy consumption of microprocessor... 
error-correcting codes | Microprocessors | ECC | Random access memory | Logic gates | low voltage operation | Resilient design | Error correction codes | error-tolerant cache | Transistors | Reliability | Testing | Error-tolerant cache | Errorcorrecting codes | Low voltage operation
Conference Proceeding
by Sun, HB and Ren, PJ and Zheng, NN and Zhang, T and Li, T
MICROPROCESSORS AND MICROSYSTEMS, ISSN 0141-9331, 06/2011, Volume 35, Issue 4, pp. 371 - 381
Radiation-induced soft error has become an emerging reliability threat to high performance microprocessor design... 
DESIGN | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | Soft error resilient | UPSET | Cache memory | COMPUTER SCIENCE, THEORY & METHODS | 3D integration | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Microprocessors and Microsystems, ISSN 0141-9331, 2011, Volume 35, Issue 4, pp. 371 - 381
Radiation-induced soft error has become an emerging reliability threat to high performance microprocessor design... 
Cache memory | Soft error resilient | 3D integration | Energy consumption | Dies | Power consumption | Architecture | Microprocessors | Soft errors | Shielding | Three dimensional
Journal Article
Proceedings of the 2013 ACM International symposium on physical design, 03/2013, pp. 50 - 57
Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations... 
resilient circuits | dynamic variations | engineering change order | timing analysis | delay padding | hold time fixing | Hold time fixing | Delay padding | Engineering change order | Resilient circuits | Dynamic variations | Timing analysis
Conference Proceeding
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 04/2013, Volume 48, Issue 4, pp. 907 - 916
... ) droops on microprocessor performance and energy efficiency. The design integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in critical paths during a V CC droop... 
clock-data compensation | variation-tolerant design | Pipelines | resilient design | adaptive clocking | Delay | Adaptive circuit | voltage variation | Sensitivity | Microprocessors | variation tolerance | resilient circuit | Transistors | voltage droop | Clocks | adaptive design | ERROR-DETECTION | POWER | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on hardware/software codesign and system synthesis, 09/2013, pp. 1 - 10
We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable floating-point units (FPUs). The... 
multi-core | approximation | OpenMP | timing error | resilient | PVT variability | floating-point | Pipelines | Registers | Approximation methods | Runtime | Computer architecture | Software | Timing | Approximation | Timing error | Multi-core | Floating-point | Resilient
Conference Proceeding
ACM Transactions on Reconfigurable Technology and Systems (TRETS), ISSN 1936-7406, 08/2014, Volume 7, Issue 3, pp. 1 - 17
This article introduces the resilient adaptive algebraic architecture that aims at adapting parallelism exploitation of a matrix multiplication algorithm in a... 
worst-case execution time | Adaptive systems | scaling | embedded systems | soft error | resilient design | real time | Embedded systems | Soft error | Scaling | Resilient design | Worst-case execution time | Real time | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | FILTERS | IMPLEMENTATION | FAULT-TOLERANCE | Design | Performance | Reliability
Journal Article
Integration (Amsterdam), ISSN 0167-9260, 2015, Volume 48, Issue 1, pp. 72 - 82
Journal Article
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