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IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 09/2014, Volume 22, Issue 9, pp. 1898 - 1908
This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications... 
embedded microprocessors | power gating | MOSFET | energy harvesting | Clamps | Rails | Logic gates | Active mode | low power | subthreshold | Threshold voltage | leakage control | Clocks | VOLTAGE | DESIGN | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC | CIRCUITS | REDUCTION | Electric potential | Reduction | Microprocessors | Chips | Chip formation | Very large scale integration | Gating and risering | Logic
Journal Article
Molecular Endocrinology, ISSN 1944-9917, 2012, Volume 26, Issue 11, pp. 1808 - 1820
Journal Article
Journal Article
International Journal of Circuit Theory and Applications, ISSN 0098-9886, 04/2016, Volume 44, Issue 4, pp. 798 - 816
Summary Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits... 
clock gating | low power | digital circuits | ASICs | power consumption | clock tree synthesis | DESIGN | DELAY-AREA DOMAIN | LOW-POWER | ENGINEERING, ELECTRICAL & ELECTRONIC | LATCHES | PLACEMENT | REDUCTION | TREE | FLIP-FLOPS | OPTIMIZATION | CIRCUIT | Availability | Automation | Synthesis | Estimating | Evolution | Gating and risering | Design analysis | Clocks
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 03/2017, Volume 25, Issue 3, pp. 1173 - 1177
Data-driven clock gated (DDCG) and multibit flip-flops (MBFFs) are two low-power design techniques that are usually treated separately. Combining these... 
Algorithm design and analysis | Layout | Merging | Very large scale integration | Logic gates | Clock gating (CG) | clock network synthesis | multibit flip-flop (MBFF) | Timing | low-power design | Clocks | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | PLACEMENT | POWER | GENERATION | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Biological Psychiatry, ISSN 0006-3223, 2008, Volume 63, Issue 11, pp. 1075 - 1083
Journal Article
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 04/2014, Volume 22, Issue 4, pp. 771 - 778
Clock gating is a predominant technique used for power saving. It is observed that the commonly used synthesis-based gating still leaves a large amount of redundant clock pulses... 
Clock gating | dynamic power reduction | clock networks | Clock networks | Dynamic power reduction | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC | Electronic design automation | Design engineering | Reduction | Very large scale integration | Hardware | Gating and risering | Flip-flops | Clocks
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 01/2009, Volume 17, Issue 1, pp. 33 - 44
Journal Article
Journal of Circuits, Systems and Computers, ISSN 0218-1266, 05/2016, Volume 25, Issue 5
Power gating (PG) is used to reduce leakage power by shutting down the power supply of the inactive block of the circuit... 
power gating | low power | within-clock | finite state machine (FSM) | Architecture | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE transactions on very large scale integration (VLSI) systems, ISSN 1557-9999, 2018, Volume 26, Issue 4, pp. 639 - 652
Journal Article