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1. Full Text An Investigation of High-Temperature (to 300 °C) Safe-Operating-Area in a High-Voltage Complementary SiGe on SOI Technology
by Omprakash, Anup P and Ha Dao and Raghunathan, Uppili S and Hanbin Ying and Chakraborty, Partha S and Babcock, Jeffrey A and Mukhopadhyay, Rajarshi and Cressler, John D
IEEE Transactions on Electron Devices, ISSN 0018-9383, 09/2017, Volume 64, Issue 9, pp. 3748 - 3755
Safe-operating-area (SOA) in a high-voltage complementary silicon-germanium (SiGe) (= n-p-n + p-n-p) on silicon-on-insulator (SOI) technology is investigated... 
Temperature | high voltage | Stress | electrothermal boundary | high temperature | mixed-mode stress | silicon-on-insulator (SOI) | Silicon germanium | Semiconductor optical amplifiers | Temperature measurement | Degradation | complementary silicon–germanium (C-SiGe) | Reliability | high-current stress | Auger recombination | reliability | complementary silicon-germanium (C-SiGe) | PHYSICS, APPLIED | ENGINEERING, ELECTRICAL & ELECTRONIC | Bipolar transistors | Temperature measurements | Usage | Analysis | Silicon | Research | Electric potential | Annealing | Semiconductor devices | Property damage | Positive temperature coefficient | Damage detection | High current | Heterojunction bipolar transistors | Augers | Silicon germanides
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2. Full Text An Investigation on the Optimization and Scaling of Complementary SiGe HBTs
by Chakraborty, P. S and Moen, K. A and Cressler, J. D
IEEE Transactions on Electron Devices, ISSN 0018-9383, 01/2013, Volume 60, Issue 1, pp. 34 - 41
We use predictive technology computer-aided design to investigate the device design challenges and optimization issues that will be necessarily encountered in... 
Performance evaluation | technology computer-aided design (TCAD) | Doping | complementary silicon-germanium (C-SiGe) | Optimization | scaling roadmap | Silicon germanium | complementary bipolar | Bipolar junction transistor (BJT) | silicon-germanium (SiGe) | Heterojunction bipolar transistors | Semiconductor process modeling | Junctions | heterojunction bipolar transistor (HBT) | PHYSICS, APPLIED | FILM SOI | PROFILE DESIGN | SIMULATION | NPN | ENGINEERING, ELECTRICAL & ELECTRONIC | BICMOS | TRANSIT-TIME ANALYSIS | SOI TECHNOLOGY | BIPOLAR-TRANSISTORS | HIGH-SPEED | Silicon compounds | Bipolar transistors | Usage | Scalability | Analysis | Innovations | Computer-aided design | Mathematical optimization | Simulation methods | Electric properties | Computer simulation | Semiconductor devices | Germanium | Devices | Computer aided design | Silicon germanides
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3. Full Text The Effects of Temperature on the Single-Event Transient Response of a High-Voltage (>30 V) Complementary SiGe-on-SOI Technology
by Omprakash, Anup P and Ildefonso, Adrian and Fleetwood, Zachary E and Tzintzarov, George N and Cardoso, Adilson S and Babcock, Jeffrey A and Mukhopadhyay, Rajarshi and Khachatrian, Ani and Warner, Jeffrey H and McMorrow, Dale and Buchner, Stephen P and Cressler, John D
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 01/2019, Volume 66, Issue 1, pp. 389 - 396
The single-event transient response of a high-voltage complementary SiGe-on-silicon-on-insulator technology is investigated along with its temperature... 
Temperature dependence | Transient response | single-event transient (SET) | complementary SiGe (C-SiGe) | high voltage | high temperature | power electronics | silicon-germanium technology | silicon-on-insulator (SOI) | Silicon germanium | Temperature measurement | Temperature sensors | single-event effects (SEEs) | TCAD | Heterojunction bipolar transistors | Transient analysis | Bias dependence | SILICON | DEPENDENCE | ENGINEERING, ELECTRICAL & ELECTRONIC | GERMANIUM | NUCLEAR SCIENCE & TECHNOLOGY | ABSORPTION | Electric potential | Temperature | Amplitudes | Semiconductor devices | Computer simulation | High temperature | High voltages | Energetic particles | Temperature effects | Technology | Heating | Voltage | Germanium | Silicon | Electric fields | Silicon germanides
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4. Full Text Single-Event Transient Response of Comparator Pre-Amplifiers in a Complementary SiGe Technology
by Ildefonso, Adrian and Lourenco, Nelson E and Fleetwood, Zachary E and Wachter, Mason T and Tzintzarov, George N and Cardoso, Adilson S and Roche, Nicolas J.-H and Khachatrian, Ani and McMorrow, Dale and Buchner, Stephen P and Warner, Jeffrey H and Paki, Pauline and Kaynak, Mehmet and Tillack, Bernd and Cressler, John D
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 01/2017, Volume 64, Issue 1, pp. 89 - 96
The single-event transient (SET) response of the pre-amplification stage of two latched comparators designed using either npn or pnp silicon-germanium... 
Performance evaluation | Latches | single-event transient | complementary SiGe | C-SiGe | PNP HBTs | Silicon germanium | radiation hardening by design (RHBD) | Measurement by laser beam | Comparators | Ring lasers | Transistors | Transient analysis | CIRCUITS | NUCLEAR SCIENCE & TECHNOLOGY | HBT | ENGINEERING, ELECTRICAL & ELECTRONIC | TPA | Uninterruptible power supply | Radiation | Voltage | Immunoglobulin E | Germanium | Silicon | Heterojunction bipolar transistors | Silicon germanides
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5. Full Text p-n-p-Based RF Switches for the Mitigation of Single-Event Transients in a Complementary SiGe BiCMOS Platform
by Song, Ickhyun and Cho, Moon-Kyu and Fleetwood, Zachary E and Gong, Yunyi and Pavlidis, Spyridon and Buchner, Stephen P and McMorrow, Dale and Paki, Pauline and Kaynak, Mehmet and Cressler, John. D
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 01/2018, Volume 65, Issue 1, pp. 391 - 398
The benefits of using p-n-p silicon-germanium (SiGe) heterojuction bipolar transistors (HBTs) in radio frequency (RF) circuits for the mitigation of... 
single-event transient (SET) | radiation hardening by design | complementary SiGe (C-SiGe) | radio frequency (RF) switch | inverse mode | pulsed laser | two-photon absorption (TPA) | Silicon germanium | Radio frequency | silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) | BiCMOS | p-n-p | single-pole single-throw (SPST) | Insertion loss | BiCMOS integrated circuits | Heterojunction bipolar transistors | Transient analysis | radiation effects | RHBD | silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) | CMOS | IRRADIATION | TECHNOLOGY | CHARGE COLLECTION | HEAVY-ION | 2-PHOTON ABSORPTION | LASER | SOI | ENGINEERING, ELECTRICAL & ELECTRONIC | CIRCUITS | NUCLEAR SCIENCE & TECHNOLOGY | X-RAY | Mitigation | Bipolar transistors | Semiconductor devices | Circuit design | Switches | Immunoglobulin E | Germanium | Silicon germanides | Spurs
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6. Full Text Total Ionizing Dose Effects on a High-Voltage (>30V) Complementary SiGe on SOI Technology
by Omprakash, Anup P and Fleetwood, Zachary E and Raghunathan, Uppili S and Ildefonso, Adrian and Cardoso, Adilson S and Lourenco, Nelson E and Babcock, Jeffrey and Mukhopadhyay, Rajarshi and En Xia Zhang and McMarr, Patrick J and Fleetwood, Daniel M and Cressler, John D
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 01/2017, Volume 64, Issue 1, pp. 277 - 284
Total ionizing dose (TID) effects are evaluated for a high-voltage (>30 V) complementary SiGe on SOI technology. Devices are irradiated with 10-keV X-rays at... 
Measurement | Radiation effects | total ionizing dose (TID) | Doping | C-SiGe | complementary SiGe | high voltage | power electronics | silicon-germanium technology | silicon-on-insulator (SOI) | Silicon germanium | TCAD | interface traps | Heterojunction bipolar transistors | Junctions | Bias dependence | High voltage | Interface traps | Silicon-on-insulator (SOI) | Power electronics | Total ionizing dose (TID) | Complementary SiGe | Silicon-germanium technology | FILM SOI | PROTON | RELIABILITY | BASE JUNCTION TRAPS | ENGINEERING, ELECTRICAL & ELECTRONIC | IMPACT | NUCLEAR SCIENCE & TECHNOLOGY | HBTS | BJTS | DEGRADATION | BIPOLAR-TRANSISTORS | Transistors | Usage | Electric potential | Traps | Technology | Voltage | Immunoglobulin E | Irradiated | Silicon | Injection | Silicon dioxide | Silicon germanides
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7. Full Text On the Transient Response of a Complementary (npn + pnp) SiGe HBT BiCMOS Technology
by Lourenco, Nelson E and Fleetwood, Zachary E and Seungwoo Jung and Cardoso, Adilson S and Chakraborty, Partha S and England, Troy D and Roche, Nicolas J.-H and Khachatrian, Ani and McMorrow, Dale and Buchner, Stephen P and Melinger, Joseph S and Warner, Jeffrey H and Paki, Pauline and Kaynak, Mehmet and Tillack, Bernd and Knoll, Dieter and Cressler, John D
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 12/2014, Volume 61, Issue 6, pp. 3146 - 3153
The single-event transient (SET) response of a third-generation bulk C-SiGe ( npn + pnp) BiCMOS platform is investigated for the first time. Pulsed-laser,... 
single-event transient (SET) | Radiation hardening (electronics) | C-SiGe | complementary-SiGe | silicon-germanium technology | Silicon germanium | nanoTCAD | Single event transients | complementary bipolar | radiation hardening | PNP heterojunction bipolar transistors | SiGe HBT | BiCMOS integrated circuits | charge collection | Heterojunction bipolar transistors | Transient analysis | single-event effects (SEE) | 4TH-GENERATION | LOGIC | ENGINEERING, ELECTRICAL & ELECTRONIC | CIRCUITS | PART-I | PROTON TOLERANCE | OPERATION | NUCLEAR SCIENCE & TECHNOLOGY | DESIGNING ELECTRONIC SYSTEMS | MITIGATION
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8. Full Text Single-Event Upset Mitigation in a Complementary SiGe HBT BiCMOS Technology
by Lourenco, Nelson E and Ildefonso, Adrian and Tzintzarov, George N and Fleetwood, Zachary E and Motoki, Keisuke and Paki, Pauline and Kaynak, Mehmet and Cressler, John D
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 01/2018, Volume 65, Issue 1, pp. 231 - 238
The single-event upset response of SiGe-based digital circuits designed in a third-generation, bulk C-SiGe ( npn + pnp ) BiCMOS platform is investigated.... 
Performance evaluation | single-event transient (SET) | current-mode logic (CML) | Shift registers | Ions | complementary SiGe (C-SiGe) | Rail to rail outputs | Silicon germanium | silicon–germanium (SiGe) technology | single-event upset (SEU) | complementary bipolar | radiation hardening | NanoTCAD | Bit error rate test (BERT) | SiGe HBT | BiCMOS integrated circuits | charge collection | heavy-ion broad-beam experiments | Heterojunction bipolar transistors | pnp heterojunction bipolar transistors (HBTs)">pnp heterojunction bipolar transistors (HBTs) | single-event effects (SEE) | TCAD modeling | silicon germanium (SiGe) technology | pnp heterojunction bipolar transistors (HBTs) | DATA RATES | LOGIC | SRAM | ENGINEERING, ELECTRICAL & ELECTRONIC | CIRCUITS | SiCe HBT | NUCLEAR SCIENCE & TECHNOLOGY | silicon germanium (SiCe) technology | Semiconductor devices | Circuit design | Computer simulation | Digital electronics | Immunoglobulin E | Mitigation | Millimeter waves | Heterojunctions | Incidence angle | Three dimensional models | Silicon germanides
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9. Full Text Modeling of broadband noise in complementary (npn + pnp) SiGe HBTs
by Banerjee, B and Venkataraman, S and Enhai Zhao and Chang-Ho Lee and Cressler, J.D and Laskar, J and El-Kareh, B and Balster, S and Yasuda, H
2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers, ISSN 1529-2517, 2005, pp. 553 - 556
We present the first comprehensive investigation of broadband noise in a complementary (npn + pnp) SiGe (C-SiGe) HBT BiCMOS technology. A base-transit time... 
Integrated circuit technology | Semiconductor device noise | Noise figure | Germanium silicon alloys | Integrated circuit noise | Isolation technology | BiCMOS integrated circuits | Heterojunction bipolar transistors | Silicon germanium | Driver circuits | Noise model | Noise | SPICE noise model | C-SiGe | Complementary bipolar technology | SiGe HBT | Bipolar technology | Complementary-SiGe | Noisy two-port, noise figure | Shot noise
Conference Proceeding
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10. Full Text Dual strained channel CMOS in FDSOI architecture: New insights on the device performance
by Le Royer, C and Cassé, M and Cooper, D and Andrieu, F and Weber, O and Brevard, L and Perreau, P and Damlencourt, J.-F and Baudot, S and Prévitali, B and Tabone, C and Allain, F and Scheiblin, P and Rauer, C and Figuet, C and Aulnette, C and Daval, N and Nguyen, B.-Y and Bourdelle, K.K and Gyani, J and Valenza, M
Solid State Electronics, ISSN 0038-1101, 11/2011, Volume 65-66, Issue 1, pp. 9 - 15
We report an original Dual Strained Channel On Insulator (DSCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/c-SiGe/(s)SOI... 
CMOS | MOSFET | Integration | High-K | Dual channel | Mobility | Silicon–germanium | Low-frequency noise | SOI | Metal gate | Access resistance | Strain | Silicon-germanium | PHYSICS, CONDENSED MATTER | PHYSICS, APPLIED | ENGINEERING, ELECTRICAL & ELECTRONIC | GATE STACK | Nitrides | Transistors | Complementary metal oxide semiconductors | Semiconductor industry | Architecture | Tin | Hafnium oxide | Stacks | Density | Channels | Gates
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11. Full Text Intelligent Integrated Systems
: Devices, Technologies, and Architectures
04/2014, Pan Stanford Series on Intelligent Nanosystems, ISBN 9789814411424, Volume 1, 516
This book gives a state-of-the-art overview by internationally recognized researchers of the architectures of breakthrough devices required for future... 
Metal oxide semiconductors, Complementary | Electromagnetics & Microwaves | Intelligent Systems | Materials Science
eBook
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12. Full Text Patent Issued for Cutting Fins and Gates in CMOS Devices
08/2017
Patents | Intellectual property | Complementary metal oxide semiconductors
Newsletter
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13. Full Text Patent Issued for Dual EPI CMOS Integration for Planar Substrates
02/2016
Periodical publishing | Patents | Epitaxy | Intellectual property | Complementary metal oxide semiconductors | Semiconductor industry
Newsletter
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