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2016 International Conference on Computing Communication Control and automation (ICCUBEA), 08/2016, pp. 1 - 4
... to reduce power dissipation effectively for 8T SRAM cell in 90nm technology using Cadence tools. 
Eight transistor (8T) | Stacking | Logic gates | SRAM cells | Static random access memory (SRAM) | Transistors | Leakage currents | Junctions | Subthreshold current | Drain induced barrier lowering (DIBL)
Conference Proceeding
IET Computers & Digital Techniques, ISSN 1751-8601, 5/2014, Volume 8, Issue 3, pp. 118 - 128
Journal Article
IEEE Transactions on Nanotechnology, ISSN 1536-125X, 07/2012, Volume 11, Issue 4, pp. 788 - 798
Journal Article
Journal Article
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