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IEEE Transactions on Computers, ISSN 0018-9340, 02/2017, Volume 66, Issue 2, pp. 368 - 374
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 06/2018, Volume 67, Issue 6, pp. 847 - 860
DRAM density scaling has become increasingly difficult due to challenges in maintaining a sufficiently high storage capacitance and a sufficiently low leakage... 
Resistance | Nonvolatile memory | Microprocessors | Random access memory | Computer architecture | main memory | STT-MRAM | Error correction codes | retention errors | Magnetic tunneling | hierarchical ECC | Magnetoresistivity | Scaling | Performance enhancement | Washing | Leakage current | Endurance | Error correction | Charge transfer | Error correcting codes
Journal Article
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 08/2018, Volume 65, Issue 8, pp. 1843 - 1850
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 09/2017, Volume 36, Issue 9, pp. 1580 - 1591
Journal Article
IEEE Micro, ISSN 0272-1732, 01/2011, Volume 31, Issue 1, pp. 11 - 19
Virtualized error checking and correcting (ECC) is a scheme that virtualizes memory-error correction. Unlike traditional uniform ECC, which provides a fixed... 
error checking and correcting | Virtual environment | fault tolerance | memory systems | ECC | Memory management | DRAM chips | Error correction codes | Error correction | Reliability | Servers | reliability | COMPUTER SCIENCE, SOFTWARE ENGINEERING | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | CODES | Memory (Computers) | Error-correcting codes | Usage | Demand | Redundant | Mapping | Tolerances | Marketing
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 06/2019, Volume 54, Issue 6, pp. 1800 - 1811
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 01/2011, Volume 60, Issue 1, pp. 20 - 34
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 06/2016, Volume 24, Issue 6, pp. 2152 - 2164
Journal Article
IEICE Transactions on Electronics, ISSN 0916-8524, 01/2015, Volume E98C, Issue 1, pp. 53 - 61
A design strategy (the required ECC strength and the judgment method of the dominant error mode) of error-prediction low-density parity-check (EP-LDPC)... 
LDPC | NAND flash memory | ECC | Error-correcting code | Low-density parity-check | low-density parity-check | CELL | ENGINEERING, ELECTRICAL & ELECTRONIC | Design engineering | Errors | Tables (data) | Interference | Strategy | Flash memory (computers) | Error correction | Acceptability
Journal Article
EURASIP Journal on Wireless Communications and Networking, ISSN 1687-1472, 12/2006, Volume 2006, Issue 1, pp. 1 - 14
Journal Article
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, ISSN 0916-8508, 12/2015, Volume E98A, Issue 12, pp. 2494 - 2504
Journal Article
IEEE Transactions on Circuits and Systems-I-Regular Papers, ISSN 1549-8328, 07/2015, Volume 62, Issue 7, p. 1804
Journal Article
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, ISSN 0916-8508, 12/2016, Volume E99A, Issue 12, pp. 2398 - 2411
Journal Article
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