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Journal Article
IEEE Transactions on Nanotechnology, ISSN 1536-125X, 03/2016, Volume 15, Issue 2, pp. 129 - 136
In this paper, we analyze the effects of aging mechanisms on the soft error susceptibility of both standard and robust latches. Particularly, we consider bias... 
Degradation | MOSFET | Soft Error | Latches | Robust Latch | Aging | Static Latch | Robustness | Threshold voltage | Standards | HIGH-PERFORMANCE | TOLERANT LATCH | PHYSICS, APPLIED | soft error | MATERIALS SCIENCE, MULTIDISCIPLINARY | NANOSCIENCE & NANOTECHNOLOGY | robust latch | SOFT | DESIGNS | ENGINEERING, ELECTRICAL & ELECTRONIC | LOW-COST | aging | Static latch | Designers
Journal Article
IEEE Transactions on Nanotechnology, ISSN 1536-125X, 2020, Volume 19, pp. 5 - 10
A pure silicon-based biristor with low latch-up voltage operation and wide latch window was studied using numerical simulations. Various parameters were... 
Biristor | Latches | Electric breakdown | latch-down voltage | Random access memory | 1T-DRAMy | Doping | latch window | latch-up voltage | capacitor-less DRAM | ZRAM | Numerical simulation | Silicon | Reliability
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 10/2015, Volume 50, Issue 10, pp. 2319 - 2330
A 7 bit 2 GS/s flash ADC fabricated in a 65nm CMOS process is presented. The proposed cascaded latch interpolation technique achieves a 4 × interpolation... 
Interpolation | Latches | Accuracy | Cascaded latch interpolation | latch interpolation | flash ADC | Ash | clock timing adjustment | Delays | interpolation ADC | Clocks | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 07/2018, Volume 53, Issue 7, pp. 1902 - 1912
A latch-type comparator with a dynamic bias pre-amplifier is implemented in a 65-nm CMOS process. The dynamic bias with a tail capacitor is simple to implement... 
Energy consumption | Latches | Strongarm | Capacitors | charge steering | SAR | Analog-to-digital converter (ADC) | Discharges (electric) | comparator | double-tail latch-type comparator | dynamic biasing | noise | Threshold voltage | latch | Transistors | Signal to noise ratio | SAR ADC | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Journal of Experimental Biology, ISSN 0022-0949, 07/2018, Volume 221, Issue 13, pp. jeb183897 - jeb183897
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 06/2011, Volume 46, Issue 6, pp. 1321 - 1336
The power consumption of wireline circuits has become increasingly more critical as the pin count and data rate rise. This paper describes a power scaling... 
decision-feedback equalizers | high-speed equalizers | Latches | Noise | Bit error rate | Decision feedback equalizers | latch sensitivity | CML latch | Sensitivity | unrolled DFE | CMOS integrated circuits | Clocks | latch offset | TRANSCEIVER | CLOCK | ENGINEERING, ELECTRICAL & ELECTRONIC | Drawing | Design engineering | CMOS | Equalizers | Power consumption | Circuits | Tradeoffs | Counting
Journal Article
Journal of Infectious Diseases, ISSN 0022-1899, 01/2018, Volume 217, Issue 1, pp. 93 - 102
Journal Article
1975, ISBN 9780909109004, xi, 441 p., [4] leaves of plates
Book
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 07/2004, Volume 39, Issue 7, pp. 1148 - 1158
Journal Article
IEEE Electron Device Letters, ISSN 0741-3106, 02/2015, Volume 36, Issue 2, pp. 186 - 188
A widely tunable variable capacitor using mechanical switching and a reversible latching mechanism was developed. This variable capacitor can increase the... 
Electrodes | Actuators | Latches | Variable capacitor | Switches Reversible latch | RF MEMS | Wide tuning range | Capacitors | Switches | Capacitance | Tuning | switches | wide tuning range | reversible mechanical latch | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
2018 New Generation of CAS (NGCAS), 11/2018, pp. 146 - 149
Dual-rail logic circuits have been used as an effective countermeasure towards a more secure circuit design. However, with technology scaling and lowering of V... 
Latches
Conference Proceeding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 09/2019, Volume 27, Issue 9, pp. 2170 - 2179
Near-threshold voltage (NTV) digital VLSI circuits, though important, have their sequential elements vulnerable to soft errors. The critical charge for a... 
Energy-efficient latches | Latches | Computational modeling | Single event upsets | soft error | radiation hardening latch | SPICE | Transistors | Transient analysis | Load modeling | single event upsets (SEU) | IMPACT | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | SUBTHRESHOLD SRAM | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 09/2016, Volume 65, Issue 9, pp. 2820 - 2834
This paper presents a set of eight novel configurations for the design of single event soft error (SE) tolerant latches. Each latch uses a three-transistor... 
Feedback loop | static latch | Latches | Soft error | hardened latch | Delays | Circuit faults | Impedance | transient fault | Transient analysis | Clocks | HIGH-PERFORMANCE | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | LOW-COST | DESIGNS | ENGINEERING, ELECTRICAL & ELECTRONIC | Logic circuitry | Logic design | Research | Impedance (Electricity) | Analysis | CMOS | Faults | Computer simulation | Specifications | Circuits | Soft errors | Delay
Journal Article
IEEE Transactions on Aerospace and Electronic Systems, ISSN 0018-9251, 11/2019, pp. 1 - 1
With the CMOS technology scaling down, radiation induced multiple-node-upsets (MNUs) that include double-node-upsets and triple-node-upsets (TNUs) are becoming... 
Radiation hardening | latch design | high-impedance-state | multiple-node-upset
Journal Article
IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 09/2019, Volume 66, Issue 9, pp. 3414 - 3422
A digitally controlled oscillator (DCO) is presented that utilizes the non-linearity of a resistor-triode combination in conjunction with a weak latch to... 
Latches | Sensitivity | Latch | Inverters | supply noise | Delays | Calibration | Phase locked loops | ring oscillator | Oscillators | PLL | PHASE | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Transactions on Computers, ISSN 0018-9340, 11/2010, Volume 59, Issue 11, pp. 1455 - 1465
Journal Article
Dianzi Jishu Yingyong, ISSN 0258-7998, 07/2019, Volume 45, Issue 7, pp. 44 - 49
A new method to realize full-pipelined SHA256 based on data storage is proposed. For the full-pipelined SHA256, only A and E need to be calculated each time... 
pipeline | mux | flipping | latch | ha256
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 06/2012, Volume 47, Issue 6, pp. 1483 - 1496
Many mobile SoC chips employ a "two-macro" approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or... 
Performance evaluation | Latches | Low VDDmin | Random access memory | Switches | nvSRAM | RRAM | Resistance | Nonvolatile memory | Memristors | memristor | memristor latch | nonvolatile SRAM | vertical-stacked | CHIP | NV-SRAM | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Microelectronics Reliability, ISSN 0026-2714, 01/2019, Volume 92, pp. 149 - 154
The single event effects (SEE) in commercial Ferroelectric Random Access Memory (FRAM) were investigated using heavy-ion and pulsed laser. Stable data upsets... 
Neutron irradiation | Single event effect | Ferroelectric random access memory | Transient micro-latch-up | IRRADIATION | PHYSICS, APPLIED | LATCH-UP | PREVENTION | NANOSCIENCE & NANOTECHNOLOGY | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
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