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Journal of Electronic Testing, ISSN 0923-8174, 10/2013, Volume 29, Issue 5, pp. 625 - 634
Journal Article
IEICE Electronics Express, ISSN 1349-2543, 08/2011, Volume 8, Issue 16, pp. 1367 - 1373
Journal Article
IEICE Electronics Express, ISSN 1349-2543, 2012, Volume 9, Issue 2, pp. 111 - 116
This paper proposes a novel scan disabling-based BIST-Aided Scan Test (BAST) scheme to reduce test data volume and test power. In this scheme, a linear... 
Design for testability (DFT) | Scan chain disabling | Test power reduction | Test data volume compression | ARCHITECTURE | scan chain disabling | design for testability (DFT) | test power reduction | test data volume compression | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING, ISSN 1016-2364, 07/2019, Volume 35, Issue 4, pp. 839 - 849
High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power... 
CIRCUITS | low power testing | DISSIPATION | SHIFT | capture power | COMPUTER SCIENCE, INFORMATION SYSTEMS | scan-based testing | scan chain | power consumption
Journal Article
Journal of the Chinese Institute of Engineers, ISSN 0253-3839, 09/2012, Volume 35, Issue 6, pp. 687 - 696
This article presents a method for test data compression aiming at simultaneously reducing test data volume and test application time for the scan sequential... 
test time reduction | scan chain disabling | compatibility | test data volume reduction | Compatibility | Scan chain disabling | Test data volume reduction | Test time reduction | TEST-DATA-COMPRESSION | COMPACT | ENGINEERING, MULTIDISCIPLINARY | POWER
Journal Article
Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology, ISSN 0367-6234, 07/2009, Volume 41, Issue 1, pp. 176 - 179
Journal Article
IEEE Transactions on Circuits and Systems II: Express Briefs, ISSN 1549-7747, 05/2007, Volume 54, Issue 5, pp. 450 - 454
A two-stage scan architecture is proposed to constrain transition propagation within a small part of scan flip-flops. Most scan flip-flops are deactivated... 
Energy consumption | Costs | Built-in self-test | clock tree test power consumption | Combinational circuits | Circuit testing | Sun | test power | Flip-flops | Energy capture | Automatic testing | Clock disabling | scan testing | test application cost | Clocks | Analysis | Clock cycles (Computers) | Deactivation | Architecture | Circuits | Mathematical analysis | Vectors (mathematics) | Constraining
Journal Article
2010 19th IEEE Asian Test Symposium, ISSN 1081-7735, 12/2010, pp. 371 - 374
With the exponential increase of transistor counts, scan design encounters several problems such as large test data volume, long test application time and high... 
test generation | low power testing | design for testability | scan chain disabling | Conferences | Logic gates | Filling | Power dissipation | Circuit faults | test volume reduction | Clocks | Testing | Design for testability | Test volume reduction | Low power testing | Scan chain disabling | Test generation
Conference Proceeding
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, ISSN 1549-7747, 05/2007, Volume 54, Issue 5, pp. 450 - 454
A two-stage scan architecture is proposed to constrain transition propagation within a small part of scan flip-flops. Most scan flip-flops are deactivated... 
clock disabling | clock tree test power consumption | scan testing | test power | test application cost | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 03/2017, Volume 25, Issue 3, pp. 942 - 953
Journal Article
在現代的晶片設計流程中,晶片測試的策略與方法是一個很重要的議題。一個有規劃的測試方法,可以大大的減少測試過程中所造成的成本消耗。而在本論文,我們將以降低測試過程中所造成的大量功率的耗費(reduce test power... 
scan cell | clique | partition | 分割 | 掃描細胞 | multiple scan chain | test pattern | 多重掃描鏈架構 | 測試樣式
Dissertation
Journal Article
Proceedings of the 45th annual Design Automation Conference, ISSN 0738-100X, 06/2008, pp. 828 - 833
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the... 
low power | scan design | test | design for test | Algorithm design and analysis | Energy consumption | System testing | Cooling | Switches | Design for Test | Circuit testing | Integrated circuit reliability | Flip-flops | Scan Design | Automatic testing | Test | Low Power | Permission
Conference Proceeding
掃描測試技術已經廣泛地使用於測試數位電路。就系統單晶片(SOC)設計而言,測試時間及功率消耗已經成為使用掃描測試技術時所遇到的兩項關鍵性的問題。在本論文中,我們將針對掃描設計電路提出可以降低掃描測試時間及功率消耗的技術。... 
降低測試功率消耗 | scan-based design | test application time reduction | 降低測試時間 | 掃描測試技術 | test power reduction
Dissertation
現今的系統晶片結合了許多電路模組和專利電路於單一晶片之中;使用的電晶體個數因而快速增加。雖然電晶體個數快速增加,使得系統晶片之功能更加強大;然而,電路中可能的故障點數目,也隨之快速增加。為了偵測這些可能的故障點,需要大量的測試資料,以及較長的掃描鏈;結果,造成測試時間過長和測試資料儲存的問題。... 
code-based compression | 掃描測試資料壓縮 | test data compression | 線性解壓縮式壓縮法 | broadcast-based compression | 廣播式壓縮法 | scan testing | linear-decompressor-based compression | 資料編碼與解碼法
Dissertation