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scan chain (184) 184
engineering, electrical & electronic (79) 79
circuit faults (62) 62
computer science, hardware & architecture (57) 57
testing (47) 47
clocks (45) 45
circuit testing (43) 43
hardware (39) 39
scan-based attack (38) 38
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design for testability (35) 35
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chains (18) 18
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test pattern generators (17) 17
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scan chain diagnosis (15) 15
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computer-aided engineering and design (10) 10
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Journal of Engineering Science and Technology Review, ISSN 1791-9320, 2013, Volume 6, Issue 2, pp. 10 - 14
Integrated Circuit has entered the era of design of the IP-based SoC (System on Chip), which makes the IP core reuse become a key issue. SoC test wrapper... 
Wrapper scan chain | Differential evolution | Soc | Wrapper Scan Chain | SoC | Differential Evolution
Journal Article
Lecture Notes in Electrical Engineering, ISSN 1876-1100, 2018, Volume 453, pp. 117 - 125
Conference Proceeding
ACM Transactions on Design Automation of Electronic Systems (TODAES), ISSN 1084-4309, 05/2017, Volume 22, Issue 3, pp. 1 - 17
Diagnosis of scan chain faults is important for yield learning and improvement. Procedures that generate tests for diagnosis of scan chain faults produce... 
Diagnostic test generation | transparent-scan | full-scan circuits | scan chain faults | Scan chain faults | Full-scan circuits | Transparent-scan | CIRCUITS | COMPUTER SCIENCE, SOFTWARE ENGINEERING | DEFECTS | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Journal Article
Journal of low power electronics and applications, ISSN 2079-9268, 2019, Volume 9, Issue 2, p. 18
Scan-based structural testing methods have seen numerous inventions in scan compression techniques to reduce TDV (test data volume) and TAT (test application... 
patterns count | scan compression | test application time | design for test | automatic test pattern generator | patterns inflation | test coverage | test data volume | scan chain
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 03/2016, Volume 24, Issue 3, pp. 1059 - 1070
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 03/2015, Volume 23, Issue 3, pp. 466 - 479
Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, the chain diagnostic resolution may still... 
Fault diagnosis | Industries | Layout | scan chain stitching | Simulated annealing | sensitive cell | Automatic test pattern generation | Routing | Circuit faults | layout | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | FAULT-DIAGNOSIS | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 02/2004, Volume 12, Issue 2, pp. 140 - 154
Journal Article
Journal of Circuits, Systems and Computers, ISSN 0218-1266, 2019, Volume 28
Nowadays, many Integrated Systems embed auxiliary on-chip instruments whose function is to perform test, debug, calibration, configuration, etc. The growing... 
IEEE 1687 | scan-chain | genetic algorithms | ATPG | microprocessor testing | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Applied mechanics and materials, ISSN 1660-9336, 09/2014, Volume 643, pp. 243 - 248
This paper presents a new built-in self-test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs.... 
Fault diagnosis | Scan chain | Pseudo-exhaustive testing | March C | BIST
Journal Article
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, ISSN 1745-1337, 12/2015, Volume E98A, Issue 12, pp. 2547 - 2555
Camellia is a block cipher jointly developed by Mitsubishi and NTT of Japan. It is designed suitable for both software and hardware implementations. One of the... 
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | Camellia | design-fortest | CRYPTOSYSTEMS | scan-based attack | scan signature | COMPUTER SCIENCE, INFORMATION SYSTEMS | side-channel attack | scan chain | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, ISSN 0916-8508, 12/2014, Volume E97A, Issue 12, pp. 2434 - 2442
Journal Article
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, ISSN 0916-8508, 2014, Volume E97-A, Issue 7, pp. 1444 - 1451
Trivium is a synchronous stream cipher using three shift registers. It is designed to have a simple structure and runs at high speed. A scan-based side-channel... 
Scan chain | Scan-based attack | Trivium | Side-channel attacks | side-channel attacks | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | scan-based attack | COMPUTER SCIENCE, INFORMATION SYSTEMS | scan chain | ENGINEERING, ELECTRICAL & ELECTRONIC | Synchronous | High speed | Information retrieval | Collection | Shift registers | Registers | Signatures | Streams
Journal Article
Open Electrical and Electronic Engineering Journal, ISSN 1874-1290, 2014, Volume 8, Issue 1, pp. 42 - 49
Recent patents and progress on scan chain balance algorithms have been reviewed. With a significant increase of the SoC (System on Chip) integration and scale,... 
SoC test | Wrapper Scan Chain | Optimization algorithm
Journal Article
2019 International SoC Design Conference (ISOCC), 10/2019, pp. 295 - 296
Scan-based test and diagnosis are important for improving yield of nanometer-scale chips. However, the scan chain can be subject to defects due to large... 
stuck-at | Diagnosis | scan chain | transition
Conference Proceeding
IEEE transactions on circuits and systems. II, Express briefs, ISSN 1549-7747, 6/2020, pp. 1 - 1
A scan architecture is the most widely used for obtaining high test coverage in manufacturing tests. However, the recent increase in circuit size has caused... 
low-power testing | Controllability | scan-based testing | scan chain stitching | design for testability (DFT)
Journal Article
Journal of Electronic Testing, ISSN 0923-8174, 6/2016, Volume 32, Issue 3, pp. 245 - 255
Journal Article
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, ISSN 0916-8508, 2009, Volume E92-A, Issue 12, pp. 3229 - 3237
Journal Article
ACM Transactions on Reconfigurable Technology and Systems (TRETS), ISSN 1936-7406, 12/2016, Volume 10, Issue 1, pp. 1 - 23
Journal Article
Procedia computer science, ISSN 1877-0509, 2020, Volume 171, pp. 2556 - 2562
Power consumed by the CUT (Circuit Under Test) during testing is a major concern in the design of DFT. Power lost due switching activity is the major part of... 
Scan-Chain | DFT | Switching activity | Power dissipation SDFF
Journal Article
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