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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, ISSN 0916-8508, 12/2018, Volume E101A, Issue 12, pp. 2262 - 2270
Journal Article
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, ISSN 0916-8508, 07/2017, Volume E100A, Issue 7, pp. 1488 - 1495
Journal Article
Integration, ISSN 0167-9260, 05/2020, Volume 72, pp. 66 - 71
Aiming at the problem that the test time is too long and the test efficiency is affected, an adaptive test patterns reordering method based on Gamma... 
Gamma distribution | Adaptive testing | Test reordering | Bayesian statistics | SCHEME | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
Wireless Personal Communications, ISSN 0929-6212, 09/2016, Volume 90, Issue 2, pp. 713 - 728
System-on-Chip is the major challenge for both design and testing engineers due to its increase in power consumption. The system consumes more power in test... 
Similarity based test vector reordering | Test data compression | Difference vector | Modified Golomb Code | Test power reduction | Don’t care fill | Don't care fill | TELECOMMUNICATIONS | Energy consumption | Embedded systems | Energy use | Data compression | Analysis | Methods | Reduction | Power consumption | Preprocessing | Similarity | Coding | Switching
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 04/2017, Volume 25, Issue 4, pp. 1497 - 1505
Journal Article
2016 IEEE 25th Asian Test Symposium (ATS), ISSN 1081-7735, 11/2016, pp. 191 - 196
Advances in semiconductor device manufacturing technology, which have enabled reduced feature size and higher integration, have resulted in a gap between the... 
Bridges | Greedy algorithms | test generation | test reordering | bridge fault | critical area | Layout | Bridge circuits | weighted fault coverage | Circuit faults | Test pattern generators
Conference Proceeding
2017 IEEE International Test Conference (ITC), ISSN 1089-3539, 10/2017, Volume 2017-, pp. 1 - 8
Advances in semiconductor device manufacturing technology, which have enabled reduced feature size and higher integration, have resulted in a gap between the... 
Bridges | Tools | Circuit faults | Test pattern generators | Layout | Bridge circuits
Conference Proceeding
ICIIECS 2015 - 2015 IEEE International Conference on Innovations in Information, Embedded and Communication Systems, 08/2015, pp. 1 - 6
Testing of VLSI circuit aims for high quality screening of the circuits by targeting on performance related faults. Excessive switching in launch and capture... 
Linear Feedback Shift Register(LFSR) | Launch Off Capture(LOC) | Automatic Test Pattern Generation (ATPG) | Launch Off Shift(LOS) | Integrated circuits | Design engineering | Faults | Algorithms | Circuits | Very large scale integration | Launches | Pattern generation
Conference Proceeding
IEICE Transactions on Electronics, ISSN 0916-8524, 2010, Volume E93-C, Issue 3, pp. 369 - 378
With the advancement of VLSI manufacturing technology entire electronic systems can be Implemented in a single intergrated circuit Due to the complexity in SoC... 
TSP | DFT | Test power | test power | ENGINEERING, ELECTRICAL & ELECTRONIC | Integrated circuits | Design engineering | Circuit design | Methodology | Benchmarks | Chains | Power dissipation | Cost engineering
Journal Article
2015 IEEE 24th Asian Test Symposium (ATS), ISSN 1081-7735, 11/2015, Volume 2016-, pp. 1 - 6
As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers.... 
Power demand | design-for-testability (DFT) | shifting power reduction | Estimation | Switches | scan based-testing | low-shift power X-fill | Automatic test pattern generation | Data models | Mathematical model | low power scan testing | ATS | Reduction | Power consumption | Circuits | Chains | Benchmarking | System on chip | Stitching
Conference Proceeding
IEICE Transactions on Electronics, ISSN 0916-8524, 2008, Volume E91-C, Issue 5, pp. 798 - 805
In this paper, we present a multiple capture approach to reducing the peak power as well as average power consumption during testing. The basic idea behind is... 
Multiple capture technique | Pattern insertion | Test pattern reordering | Capture violation problem | CIRCUITS | pattern insertion | capture violation problem | test pattern reordering | multiple capture technique | ENGINEERING, ELECTRICAL & ELECTRONIC | Power consumption | Circuits | Testing time | Electronics | Insertion | Benchmarking | Chains | Time measurements
Journal Article
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, ISSN 1598-1657, 2016, Volume 16, Issue 5, pp. 582 - 594
Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm... 
Code–based test data compression | Test data compression | Low power testing | Scan chain reordering | Routing congestion | code-based test data compression | low power testing | routing congestion | PHYSICS, APPLIED | scan chain reordering | TIME | ENGINEERING, ELECTRICAL & ELECTRONIC | 전기공학
Journal Article
Indian Journal of Science and Technology, ISSN 0974-6846, 10/2016, Volume 9, Issue 38
Journal Article
2018 4th International Conference on Computing Communication and Automation (ICCCA), 12/2018, pp. 1 - 6
Test power dissipation is way higher than normal mode power dissipation due to extensive switching activity, which affects the reliability of the device.... 
Genetic Algorithmb Simulated Annealing | Sociology | Local optimum | Switches | switching activity | Power dissipation | Test vector Re-ordering | Fitness function | Statistics | Optimization | Biological cells | Genetic algorithms
Conference Proceeding
26th IEEE VLSI Test Symposium (vts 2008), ISSN 1093-0167, 04/2008, pp. 147 - 154
This paper proposes a scan-cell reordering scheme, named ROBPR, to reduce the signal transitions during test mode while preserving the don't-care bits in the... 
Energy consumption | reordering | signal transitions | Electronic equipment testing | Test pattern generators | Circuit testing | Centralized control | scan-chain | correlation | Signal generators | Power generation | Signal design | Power engineering and energy | Clocks
Conference Proceeding
International Journal of High Performance Systems Architecture, ISSN 1751-6528, 2016, Volume 6, Issue 1, pp. 51 - 60
An algorithm of test pattern generation for multiple faults is proposed using the zero suppressed decision diagrams (ZBDDs). Test pattern generation plays a... 
Binary decision diagram | Zero suppressed decision diagrams | BDD | Test pattern generation | Test power reduction | Multiple faults | ZBDDs | Reordering algorithm | Design engineering | Faults | Algorithms | Power consumption | Chips (electronics) | Chips | Architecture (computers) | Test pattern generators
Journal Article
Journal of Electronic Testing, ISSN 0923-8174, 2/2015, Volume 31, Issue 1, pp. 43 - 52
A power efficient BIST TPG method is proposed to reduce test power dissipation during scan testing. Before the test patterns are injected into scan chain, the... 
Engineering | Test data compression | Don’t care bit adjusting | Computer-Aided Engineering (CAD, CAE) and Design | Hamming distance reordering | Area overhead | Scan-in test power dissipation | Circuits and Systems | Electrical Engineering
Journal Article
by Yuan, HY and Guo, K and Sun, X and Mei, JP and Song, HY
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, ISSN 0923-8174, 02/2015, Volume 31, Issue 1, pp. 43 - 52
Journal Article
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