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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 04/2015, Volume 34, Issue 4, pp. 554 - 562
Journal Article
Proceedings of the IEEE, ISSN 0018-9219, 01/2009, Volume 97, Issue 1, pp. 43 - 48
Journal Article
IEEE Transactions on Electromagnetic Compatibility, ISSN 0018-9375, 10/2017, Volume 59, Issue 5, pp. 1541 - 1548
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 04/2018, Volume 65, Issue 4, pp. 1473 - 1479
Journal Article
Journal Article
IEEE Electron Device Letters, ISSN 0741-3106, 10/2018, Volume 39, Issue 10, pp. 1493 - 1496
A new vertical field-effect transistor (FET) has been fabricated inside a through silicon VIA (TSV). Front side and backside of a 200-... 
3D Integration | vertical FET | TSV | Logic gates | ALD | Silicon | layout camouflaging | Transistors | Through-silicon vias | Surface treatment | TSVFET | Aluminum oxide | ENGINEERING, ELECTRICAL & ELECTRONIC | Integrated circuits | Semiconductor devices | Atomic layer deposition | Field effect transistors | Interconnections | Silicon dioxide
Journal Article
Microelectronic Engineering, ISSN 0167-9317, 01/2019, Volume 205, pp. 20 - 25
The copper electrochemical deposition ( ) filling capability of high aspect ratio through silicon vias ( ) and homogeneity over 300 mm wafers were investigated... 
Copper TSV fill | Through-silicon via | 3D-integration | Atomic layer deposition | Ruthenium seed layer | Tantalum nitride diffusion barrier | PHYSICS, APPLIED | DEPOSITION | NANOSCIENCE & NANOTECHNOLOGY | ENGINEERING, ELECTRICAL & ELECTRONIC | FILMS | GROWTH | OPTICS | ELECTRODEPOSITION
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 01/2012, Volume 47, Issue 1, pp. 107 - 116
A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4... 
through-silicon vias | DRAM chips | CMOS memory integrated circuits | Correlation | Stacking | Circuits | Packages | Chips | Bandwidth | Blocking | Channels
Journal Article
IEEE Transactions on Components, Packaging and Manufacturing Technology, ISSN 2156-3950, 02/2011, Volume 1, Issue 2, pp. 208 - 219
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 04/2016, Volume 24, Issue 4, pp. 1503 - 1514
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 12/2015, Volume 23, Issue 12, pp. 3129 - 3132
Through-silicon-via (TSV) offers vertical connections for 3-D ICs. Due to its large dimensions and nonideal etching process, TSVs layout needs to be carefully... 
3-D IC | Wires | Layout | Delays | Through-silicon vias | Current density | Optimization | Passivation | tapered through-silicon-via (TSV) | optimization | tapered through-siliconvia (TSV) | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | VIAS | ENGINEERING, ELECTRICAL & ELECTRONIC | Dynamic programming
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 12/2014, Volume 33, Issue 12, pp. 1900 - 1913
Journal Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, 01/2019, Volume 38, Issue 1, pp. 190 - 194
Journal Article
Journal of the Electrochemical Society, ISSN 0013-4651, 2019, Volume 166, Issue 1, pp. D3226 - D3231
A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon... 
ELECTROCHEMISTRY | DAMASCENE TRENCHES | SILICON-VIAS | DEPOSITION | MATERIALS SCIENCE, COATINGS & FILMS | HIGH-ASPECT-RATIO | INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CHEMISTRY | TSV | 3D Interconnects | Microelectronics - Semiconductor Processing | Through Silicon Vias | MEMs | Electrodeposition - Copper
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 01/2011, Volume 46, Issue 1, pp. 293 - 307
In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is... 
network-on-chip | thermal behavior | Stacking | Electrostatic discharge | mechanical stress | 3-D | noise coupling | ESD | Capacitance | CU TSV | Copper | Reliability | Arrays | Through-silicon vias | SILICON | INTEGRATION TECHNOLOGY | VIAS | ENGINEERING, ELECTRICAL & ELECTRONIC | Studies | Design engineering | Noise levels | Chips | High speed | Digital circuits | Failure | Gates (circuits) | MOS devices
Journal Article
IEEE Transactions on Electron Devices, ISSN 0018-9383, 12/2015, Volume 62, Issue 12, pp. 4161 - 4168
Along with extensive applications of through-silicon vias (TSVs) in 3-D systems, such as digital, logic, and memory modules, the accurate modeling of coupling... 
through-silicon vias (TSVs) | MOS effect | Doping | Capacitance | Silicon | Coupling capacitance | Through-silicon vias | Substrates | PHYSICS, APPLIED | THROUGH-SILICON | MODEL | VIAS | TECHNOLOGY | ENGINEERING, ELECTRICAL & ELECTRONIC | Electric potential | Metal oxide semiconductors | Joining | Logic | Devices | Electric fields | Three dimensional
Journal Article
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 06/2013, Volume 48, Issue 6, pp. 1521 - 1529
TSV-based 3D die-stacking technology enables the reuse of pre-designed, pre-tested logic dies stacked with multiple memory layers ( N STACK ) in various... 
3D Memory | Three-dimensional displays | Poles and towers | Wires | Random access memory | 3D-IC | System-on-chip | Delays | Through-silicon vias | SRAM | through-silicon via (TSV) | DESIGN | PROCESSOR | 3-D | DRAM | CACHE | TECHNOLOGY | SRAMS | ENGINEERING, ELECTRICAL & ELECTRONIC | Load | Electric potential | Dies | Swing | Data storage | Stacks | Logic | Three dimensional | Sorting
Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 01/2017, Volume 25, Issue 1, pp. 308 - 318
In this paper, we present a novel through-silicon-via (TSV)-based 3-D inductor structure with ground TSV shielding for better noise performance. In addition, a... 
Q-factor | Inductance | Solid modeling | 3-D full wave simulation | 3-D inductor | crosstalk | through-silicon-via (TSV) shielding | Inductors | Through-silicon vias | Integrated circuit modeling | Substrates | SPIRAL INDUCTORS | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC | Three dimensional models | Crosstalk
Journal Article
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