X
Search Filters
Format Format
Subjects Subjects
Subjects Subjects
X
Sort by Item Count (A-Z)
Filter by Count
engineering, electrical & electronic (29) 29
physics, applied (25) 25
physics, condensed matter (21) 21
devices (15) 15
silicon (14) 14
transistors (14) 14
mosfets (13) 13
threshold voltage (13) 13
logic gates (11) 11
silicon-on-insulator (11) 11
cmos (10) 10
channels (8) 8
fdsoi (8) 8
microelectronics (8) 8
mos-fet (8) 8
circuit components (7) 7
metal oxide semiconductor field effect transistors (7) 7
oxides (7) 7
soi-technik (7) 7
engineering sciences (6) 6
micro and nanotechnologies (6) 6
oxid (6) 6
transistor (6) 6
ultra-thin body (6) 6
dielectric films (5) 5
finfets (5) 5
fully depleted (5) 5
integrated circuits (5) 5
mosfet (5) 5
nanoscience & nanotechnology (5) 5
soi (5) 5
thin films (5) 5
ultra-thin box (5) 5
ultra-thin soi (5) 5
analysis (4) 4
buried oxide (4) 4
complementary metal oxide semiconductors (4) 4
depletion (4) 4
electronics (4) 4
finfet (4) 4
gate (4) 4
gates (4) 4
mobility (4) 4
mos devices (4) 4
performance (4) 4
schwellenspannung (4) 4
sige (4) 4
silicon films (4) 4
soi mosfets (4) 4
standards (4) 4
substrates (4) 4
technology application (4) 4
ultra thin body and box (4) 4
analog figures of merit (3) 3
asymmetry (3) 3
back plane (3) 3
back-biasing (3) 3
bias (3) 3
cmos integrated circuits (3) 3
cmos technology (3) 3
degradation (3) 3
doping (3) 3
electric properties (3) 3
filmdicke (3) 3
fully depleted soi (3) 3
ground plane (3) 3
impact (3) 3
komplementäre mos-schaltung (3) 3
materials science, multidisciplinary (3) 3
multi-vt (3) 3
optics (3) 3
physics (3) 3
radio frequency (3) 3
semiconductor chips (3) 3
son (3) 3
spannung (3) 3
strain (3) 3
subthreshold slope (3) 3
technology (3) 3
total ionizing dose (3) 3
transconductance (3) 3
ultra-thin body and buried oxide fdsoi (3) 3
ultra-thin-body (3) 3
variability (3) 3
well implant (3) 3
[spi.nano]engineering sciences [physics]/micro and nanotechnologies/microelectronics (2) 2
body biasing (2) 2
box (2) 2
carrier mobility (2) 2
computer-aided design (2) 2
cs: common source (2) 2
cut-off (2) 2
cutoff frequency (2) 2
depleted soi mosfets (2) 2
design (2) 2
drains (2) 2
electron (2) 2
elektrische grösse (2) 2
energy efficiency (2) 2
engineering and technology (2) 2
more...
Language Language
Publication Date Publication Date
Click on a bar to filter by decade
Slide to change publication date range


Solid-State Electronics, ISSN 0038-1101, 03/2016, Volume 117, pp. 37 - 59
This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the... 
Multi-Vt | Ultra-thin BOX and body FDSOI | Strain enhancement | Back-biasing | FDSOI | PHYSICS, CONDENSED MATTER | PHYSICS, APPLIED | FLUCTUATIONS | MOSFETS | ENGINEERING, ELECTRICAL & ELECTRONIC | Silicon | Nanotechnology | Complementary metal oxide semiconductors
Journal Article
Solid State Electronics, ISSN 0038-1101, 03/2016, Volume 117, pp. 37 - 59
This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the... 
Multi-Vt | Ultra-thin BOX and body FDSOI | Strain enhancement | FDSOI | Back-biasing | Silicon
Journal Article
IEEE Electron Device Letters, ISSN 0741-3106, 03/2012, Volume 33, Issue 3, pp. 318 - 320
The impact of body-thickness scaling on strain-induced carrier-mobility enhancement in thin-body CMOSFETs with high-k/metal gate stacks, based on... 
strain | ultra thin body and BOX | high-k/metal gate | High K dielectric materials | FinFET | Logic gates | fully depleted silicon-on-insulator (FD-SOI) | FinFETs | Silicon | Carrier mobility | Stress | COULOMB SCATTERING | TRANSPORT | ENGINEERING, ELECTRICAL & ELECTRONIC
Journal Article
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), ISSN 2324-8432, 10/2013, pp. 168 - 173
Ultra-Thin Body and BOX Fully-Depleted SOI (UTBB FD-SOI) technology is one of two candidate technologies for replacing Bulk technology at sub-20 nm nodes.... 
Ultra-Thin Body and BOX | multi-VT | Doping | energy efficiency | Logic gates | low voltage | FD-SOI | Silicon | Transistors | Tuning | Standards | MOS devices
Conference Proceeding
Proceedings of the Conference on design, automation and test in europe, ISSN 1530-1591, 03/2013, pp. 613 - 618
Todays' MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a... 
adaptive architectures | low voltage | ultra thin body and box | FDSOI | energy efficiency | Low voltage | Random access memory | Doping | Ultra Thin Body and Box | Logic gates | Energy efficiency | Transistors | Standards | Adaptive architectures
Conference Proceeding
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 10/2018, pp. 1 - 2
This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm... 
ultra-thin boby and box (UTBB) | Meetings | Silicon-on-insulator | Manuals | back bias | FD SOI | Microelectronics | Electron devices | Substrates | Back bias | Ultra-thin boby and box (UTBB)
Conference Proceeding
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 12/2014, Volume 61, Issue 6, pp. 3023 - 3029
Journal Article
Solid State Electronics, ISSN 0038-1101, 2009, Volume 53, Issue 7, pp. 735 - 740
Journal Article
Journal of Nanoelectronics and Optoelectronics, ISSN 1555-130X, 2016, Volume 11, Issue 4, pp. 472 - 476
In the present paper, the scaling limit of underlap fully depleted strained ultra thin body silicon-on-insulator MOSFET (SUL) has been evaluated for the first... 
Ultra Thin Body Silicon-On-Insulator | Underlap Structure | Quantum-Mechanical Effects | Scalability | Short Channel Effects | Strained Channel | PHYSICS, APPLIED | NANOSCIENCE & NANOTECHNOLOGY | ENGINEERING, ELECTRICAL & ELECTRONIC | Depletion | Quantum mechanics | Thin bodies | Leakage current | Mathematical models | Devices | MOSFETs | Gates
Journal Article
2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013, 2013, pp. 1 - 2
The SOI technology has already demonstrated intrinsic resistance to transient radiation effects due to the dielectric isolation provided by the buried oxide.... 
Extra-Thin SOI (ETSOI) | Total Ionizing Dose (TID) | Silicon-On-Insulator (SOI) | Single-Event Effects (SEE) | FinFET | Fully Depleted (FD) | multiple-gate FET | Single-Event Transient (SET) | Ultra-Thin BOX and Body (UTBB) | Oxides | Nanostructure | Depletion | Microelectronics | Dielectrics | Devices
Conference Proceeding
2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), ISSN 1550-8781, 10/2014, pp. 1 - 4
This paper describes for the first time the high frequency performance characterization of a production 28-nm ultra-thin-body-and-BOX (UTBB) fully-depleted... 
MOSFET | Current measurement | Layout | MOSFET circuits | Logic gates | CMOS technology | CMOS integrated circuits | MAG | Ultra-thin-body | Cutoff frequency | Back gate | SOI MOSFETs | Transconductance
Conference Proceeding
IEEE TRANSACTIONS ON ELECTRON DEVICES, ISSN 0018-9383, 08/2011, Volume 58, Issue 8, pp. 2473 - 2482
This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage V T platform for digital circuits... 
ultra-thin body and buried oxide (BOX) FDSOI (UTBB FDSOI) | HIGH-K | PHYSICS, APPLIED | SILICON | THIN BOX | well implant | MOSFETS | ENGINEERING, ELECTRICAL & ELECTRONIC | GROUND PLANE | METAL GATE | multi-V-T | Back plane (BP) | TECHNOLOGY | CMOS | Platforms | Circuit design | Threshold voltage | Devices | Channels | Digital circuits | Gates (circuits)
Journal Article
International Conference on Advanced Technologies for Communications, ISSN 2162-1039, 12/2018, Volume 2018-, pp. 382 - 386
Conference Proceeding
Solid State Electronics, ISSN 0038-1101, 04/2012, Volume 70, pp. 50 - 58
Journal Article
Science China Information Sciences, ISSN 1674-733X, 6/2016, Volume 59, Issue 6, pp. 1 - 15
Fully depleted SOI (FDSOI) has become a viable technology not only for continued CMOS scaling to 22 nm node and beyond but also for improving the performances... 
foundry | strain engineering | FDSOI | Computer Science | design | low power | Information Systems and Communication Service | variability | IoT | ULTRA-THIN-BODY | COMPUTER SCIENCE, INFORMATION SYSTEMS | VLIW DSP | ENGINEERING, ELECTRICAL & ELECTRONIC | CMOS | GHZ | DEVICES | GATE LENGTH
Journal Article
2018 International Conference on Advanced Technologies for Communications (ATC), 10/2018, pp. 382 - 386
Fully depleted silicon-on-insulator (FD-SOI) semiconductor technology enables scalability of planar semiconductors devices with unique body-bias capability.... 
Radio frequency | buried oxide (BOX) | Silicon-on-insulator | Fully depleted SOI | ultra-thin SOI | CMOS technology | Silicon | Transistors | Reliability | Substrates | body biasing
Conference Proceeding
No results were found for your search.

Cannot display more than 1000 results, please narrow the terms of your search.