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engineering, electrical & electronic (29) 29
physics, applied (25) 25
physics, condensed matter (21) 21
devices (15) 15
silicon (14) 14
transistors (14) 14
mosfets (13) 13
threshold voltage (13) 13
logic gates (11) 11
silicon-on-insulator (11) 11
cmos (10) 10
channels (8) 8
fdsoi (8) 8
microelectronics (8) 8
mos-fet (8) 8
circuit components (7) 7
metal oxide semiconductor field effect transistors (7) 7
oxides (7) 7
soi-technik (7) 7
engineering sciences (6) 6
micro and nanotechnologies (6) 6
oxid (6) 6
transistor (6) 6
ultra-thin body (6) 6
dielectric films (5) 5
finfets (5) 5
fully depleted (5) 5
integrated circuits (5) 5
mosfet (5) 5
nanoscience & nanotechnology (5) 5
soi (5) 5
thin films (5) 5
ultra-thin box (5) 5
ultra-thin soi (5) 5
analysis (4) 4
buried oxide (4) 4
complementary metal oxide semiconductors (4) 4
depletion (4) 4
electronics (4) 4
finfet (4) 4
gate (4) 4
gates (4) 4
mobility (4) 4
mos devices (4) 4
performance (4) 4
schwellenspannung (4) 4
sige (4) 4
silicon films (4) 4
soi mosfets (4) 4
standards (4) 4
substrates (4) 4
technology application (4) 4
ultra thin body and box (4) 4
analog figures of merit (3) 3
asymmetry (3) 3
back plane (3) 3
back-biasing (3) 3
bias (3) 3
cmos integrated circuits (3) 3
cmos technology (3) 3
degradation (3) 3
doping (3) 3
electric properties (3) 3
filmdicke (3) 3
fully depleted soi (3) 3
ground plane (3) 3
impact (3) 3
komplementäre mos-schaltung (3) 3
materials science, multidisciplinary (3) 3
multi-vt (3) 3
optics (3) 3
physics (3) 3
radio frequency (3) 3
semiconductor chips (3) 3
son (3) 3
spannung (3) 3
strain (3) 3
subthreshold slope (3) 3
technology (3) 3
total ionizing dose (3) 3
transconductance (3) 3
ultra-thin body and buried oxide fdsoi (3) 3
ultra-thin-body (3) 3
variability (3) 3
well implant (3) 3
[spi.nano]engineering sciences [physics]/micro and nanotechnologies/microelectronics (2) 2
body biasing (2) 2
box (2) 2
carrier mobility (2) 2
computer-aided design (2) 2
cs: common source (2) 2
cut-off (2) 2
cutoff frequency (2) 2
depleted soi mosfets (2) 2
design (2) 2
drains (2) 2
electron (2) 2
elektrische grösse (2) 2
energy efficiency (2) 2
engineering and technology (2) 2
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1. Full Text Common source power amplifier design for 5G application in 28-nm UTBB FD-SOI technology
by Mohsen, Ali and Ayoub, Mohammad Jaafar and Alloush, Mostafa and Harb, Adnan and Deltimple, Nathalie and Serhane, Abraham
AEUE - International Journal of Electronics and Communications, ISSN 1434-8411, 11/2018, Volume 96, pp. 273 - 278
The telecommunication market examines a highly growing demand for RF mobile devices where low latency and high performance are ongoing improvement. The power... 
FBB: forward body bias | Psat: saturated output power | UTBB FD-SOI: ultra-thin body and box fully depleted silicon on insulator | PAE: power added efficiency | mm-wave PA: milli-meter wave power amplifier | CS: common source | saturated output power | ultra-thin body and box fully | P-sa1: saturated output power | depleted silicon on insulator | amplifier | TELECOMMUNICATIONS | mm-wave PA: milli-meter wave power | UTBB FD-S01 | ENGINEERING, ELECTRICAL & ELECTRONIC | Mobile devices | Transistors | Power amplifiers | Ocean energy resources
Journal Article
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2. Full Text Class AB vs. class J 5G power amplifier in 28-nm UTBB FD-SOI technology for high efficiency operation
by Ayoub, Mohammad Jaafar and Alloush, Mostafa and Mohsen, Ali and Harb, Adnan and Deltimple, Nathalie and Serhane, Abraham
2017 29th International Conference on Microelectronics (ICM), 12/2017, Volume 2017-, pp. 1 - 4
Nowadays, technological demands are exponentially and rapidly growing. The telecommunication market examines a growing demand for RF mobile devices where high... 
5G mobile communication | Psat: Saturated output power | CS: Common Source | Topology | Radio frequency | Network topology | Power amplifiers | UTBB FD-SOI | FBB: Forward Body Bias | mm-wave PA: milli-meter wave Power Amplifier | Ultra-Thin Body and Box Fully Depleted Silicon on Insulator | Transistors | PAE: Power Added Efficiency | Gain | CS: Common source | Mm-wave PA: Milli-meter wave power amplifier | PAE: Power added efficiency | FBB: Forward body bias | Ultra-thin body and box fully depleted silicon on insulator
Conference Proceeding
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3. Full Text Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond
by Doris, B and Desalvo, B and Cheng, K and Morin, P and Vinet, M
Solid-State Electronics, ISSN 0038-1101, 03/2016, Volume 117, pp. 37 - 59
This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the... 
Multi-Vt | Ultra-thin BOX and body FDSOI | Strain enhancement | Back-biasing | FDSOI | PHYSICS, CONDENSED MATTER | PHYSICS, APPLIED | FLUCTUATIONS | MOSFETS | ENGINEERING, ELECTRICAL & ELECTRONIC | Silicon | Nanotechnology | Complementary metal oxide semiconductors
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4. Full Text Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28nm node and beyond
by Doris, B and DeSalvo, B and Cheng, K and Morin, P and Vinet, M
Solid State Electronics, ISSN 0038-1101, 03/2016, Volume 117, pp. 37 - 59
This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the... 
Multi-Vt | Ultra-thin BOX and body FDSOI | Strain enhancement | FDSOI | Back-biasing | Silicon
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5. Full Text Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs
by Nuo Xu and Ho, Byron and Andrieu, F and Smith, L and Bich-Yen Nguyen and Weber, O and Poiroux, T and Faynot, O and Tsu-Jae King Liu
IEEE Electron Device Letters, ISSN 0741-3106, 03/2012, Volume 33, Issue 3, pp. 318 - 320
The impact of body-thickness scaling on strain-induced carrier-mobility enhancement in thin-body CMOSFETs with high-k/metal gate stacks, based on... 
strain | ultra thin body and BOX | high-k/metal gate | High K dielectric materials | FinFET | Logic gates | fully depleted silicon-on-insulator (FD-SOI) | FinFETs | Silicon | Carrier mobility | Stress | COULOMB SCATTERING | TRANSPORT | ENGINEERING, ELECTRICAL & ELECTRONIC
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6. Full Text Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology
by Pelloux-Prayer, Bertrand and Valentian, Alexandre and Giraud, Bastien and Thonnart, Yvain and Noel, Jean-Philippe and Flatresse, Philippe and Beigne, Edith
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), ISSN 2324-8432, 10/2013, pp. 168 - 173
Ultra-Thin Body and BOX Fully-Depleted SOI (UTBB FD-SOI) technology is one of two candidate technologies for replacing Bulk technology at sub-20 nm nodes.... 
Ultra-Thin Body and BOX | multi-VT | Doping | energy efficiency | Logic gates | low voltage | FD-SOI | Silicon | Transistors | Tuning | Standards | MOS devices
Conference Proceeding
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7. Full Text Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs
by Beigne, E and Valentian, A and Giraud, B and Thomas, O and Benoist, T and Thonnart, Y and Bernard, S and Moritz, G and Billoint, O and Maneglia, Y and Flatresse, P and Noel, J and Abouzeid, F and Pelloux-Prayer, B and Grover, A and Clerc, S and Roche, P and Le Coz, J and Engels, S and Wilson, R
Proceedings of the Conference on design, automation and test in europe, ISSN 1530-1591, 03/2013, pp. 613 - 618
Todays' MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a... 
adaptive architectures | low voltage | ultra thin body and box | FDSOI | energy efficiency | Low voltage | Random access memory | Doping | Ultra Thin Body and Box | Logic gates | Energy efficiency | Transistors | Standards | Adaptive architectures
Conference Proceeding
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8. Full Text Insights to the Scaling Impact on Back-Gate Biasing for FD SOI MOSFETs
by Chang, Ming-Yu and Wang, Li-Jing and Chiang, Meng-Hsueh
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 10/2018, pp. 1 - 2
This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm... 
ultra-thin boby and box (UTBB) | Meetings | Silicon-on-insulator | Manuals | back bias | FD SOI | Microelectronics | Electron devices | Substrates | Back bias | Ultra-thin boby and box (UTBB)
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9. Full Text Total Ionizing Dose Effects Mitigation Strategy for Nanoscaled FDSOI Technologies
by Gaillardin, M and Martinez, M and Paillet, P and Raine, M and Andrieu, F and Faynot, O and Thomas, O
IEEE Transactions on Nuclear Science, ISSN 0018-9499, 12/2014, Volume 61, Issue 6, pp. 3023 - 3029
We propose a TID effect hardening strategy for nanoscaled ultra-thin BOX and body SOI technologies. Experiments performed on NMOS and PMOS transistors... 
TID mitigation technique | Radiation effects | MOSFET | Fully depleted | Radiation hardening (electronics) | silicon-on insulator (SOI) | total ionizing dose (TID) | Silicon-on-insulator | ultra-thin box | ultra-thin box and body (UTBB) | Threshold voltage | Integrated circuit modeling | ultra-thin SOI (UTSOI) | BIAS | SOI | RADIATION | ENGINEERING, ELECTRICAL & ELECTRONIC | IRRADIATION | NUCLEAR SCIENCE & TECHNOLOGY | DEVICES | THRESHOLD VOLTAGE
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10. Full Text Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution
by Bidal, G and Loubet, N and Fenouillet-Beranger, C and Denorme, S and Perreau, P and Fleury, D and Clement, L and Laviron, C and Leverd, F and Gouraud, P and Barnola, S and Beneyton, R and Torres, A and Duluard, C and Chapon, J.D and Orlando, B and Salvetat, T and Grosjean, M and Deloffre, E and Pantel, R and Dutartre, D and Monfray, S and Ghibaudo, G and Boeuf, F and Skotnicki, T
Solid State Electronics, ISSN 0038-1101, 2009, Volume 53, Issue 7, pp. 735 - 740
This work proposes a planar fully depleted “folded” technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance... 
Short-channel Effects | UTB 2 | SON | Fully-depleted | Ultra thin BOX | Wafer orientation | Ultra thin body | Folded FET | DIBL | Subthreshold slope | UTB | PHYSICS, CONDENSED MATTER | PHYSICS, APPLIED | UTB2 | MOSFETS | ENGINEERING, ELECTRICAL & ELECTRONIC | CMOS | DEVICES | Technology application | Epitaxy | Depletion | Brackets | Wafers | Electronics | Footprints | Oxides | Devices | Channels | Condensed Matter | Micro and nanotechnologies | Microelectronics | Engineering Sciences | Physics | Other
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11. Novel FDSOI band-modulation device: Z2-FET with Dual Ground Planes
by El Dirani, H and Fonteneau, P and Solaro, Y and Ferrari, P and Cristoloveanu, S
European Solid-State Device Research Conference, ISSN 1930-8876, 10/2016, Volume 2016-, pp. 210 - 213
Sharp Switch | Fully Depleted SOI (FDSOI) | Zero Impact Ionization and Zero Subthreshold Slope FET | 1T-DRAM | Dual Ground Planes | Electro-Static Discharge (ESD) | Ultra-Thin Body and BOX (UTBB) | Hysteresis
Conference Proceeding
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12. Scalability projection of underlap fully depleted strained ultra thin body silicon-on-insulator MOSFETs using quantum potential simulations
by Sharma, Rajneesh and Rana, Ashwani K
Journal of Nanoelectronics and Optoelectronics, ISSN 1555-130X, 2016, Volume 11, Issue 4, pp. 472 - 476
In the present paper, the scaling limit of underlap fully depleted strained ultra thin body silicon-on-insulator MOSFET (SUL) has been evaluated for the first... 
Ultra Thin Body Silicon-On-Insulator | Underlap Structure | Quantum-Mechanical Effects | Scalability | Short Channel Effects | Strained Channel | PHYSICS, APPLIED | NANOSCIENCE & NANOTECHNOLOGY | ENGINEERING, ELECTRICAL & ELECTRONIC | Depletion | Quantum mechanics | Thin bodies | Leakage current | Mathematical models | Devices | MOSFETs | Gates
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13. Radiation effects in advanced SOI devices: New insights into Total Ionizing Dose and Single-Event Effects
by Gaillardin, M and Raine, M and Paillet, P and Martinez, M and Marcandella, C and Girard, S and Duhamel, O and Richard, N and Andrieu, F and Barraud, S and Faynot, O
2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013, 2013, pp. 1 - 2
The SOI technology has already demonstrated intrinsic resistance to transient radiation effects due to the dielectric isolation provided by the buried oxide.... 
Extra-Thin SOI (ETSOI) | Total Ionizing Dose (TID) | Silicon-On-Insulator (SOI) | Single-Event Effects (SEE) | FinFET | Fully Depleted (FD) | multiple-gate FET | Single-Event Transient (SET) | Ultra-Thin BOX and Body (UTBB) | Oxides | Nanostructure | Depletion | Microelectronics | Dielectrics | Devices
Conference Proceeding
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14. Full Text Multi-VT UTBB FDSOI device architectures for low-power CMOS circuit
by Noel, Jean-Philippe and Thomas, Olivier and Jaud, Marie-Anne and Weber, Olivier and Poiroux, Thierry and Fenouillet-Beranger, Claire and Rivallin, Pierrette and Scheiblin, Pascal and Andrieu, François and Vinet, Maud and Rozeau, Olivier and Boeuf, Frédéric and Faynot, Olivier and Amara, Amara
IEEE Transactions on Electron Devices, ISSN 0018-9383, 2011, Volume 58, Issue 8, pp. 2473 - 2482
Back plane (BP) | well implant | ultra-thin body and buried oxide (BOX) FDSOI (UTBB FDSOI)
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15. Full Text Characterization of the High Frequency Performance of 28-nm UTBB FDSOI MOSFETs as a Function of Backgate Bias
by Shopov, Stefan and Voinigescu, Sorin P
2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), ISSN 1550-8781, 10/2014, pp. 1 - 4
This paper describes for the first time the high frequency performance characterization of a production 28-nm ultra-thin-body-and-BOX (UTBB) fully-depleted... 
MOSFET | Current measurement | Layout | MOSFET circuits | Logic gates | CMOS technology | CMOS integrated circuits | MAG | Ultra-thin-body | Cutoff frequency | Back gate | SOI MOSFETs | Transconductance
Conference Proceeding
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16. Full Text Multi-V-T UTBB FDSOI Device Architectures for Low-Power CMOS Circuit
by Noel, JP and Thomas, O and Jaud, MA and Weber, O and Poiroux, T and Fenouillet-Beranger, C and Rivallin, P and Scheiblin, P and Andrieu, F and Vinet, M and Rozeau, O and Boeuf, F and Faynot, O and Amara, A
IEEE TRANSACTIONS ON ELECTRON DEVICES, ISSN 0018-9383, 08/2011, Volume 58, Issue 8, pp. 2473 - 2482
This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage V T platform for digital circuits... 
ultra-thin body and buried oxide (BOX) FDSOI (UTBB FDSOI) | HIGH-K | PHYSICS, APPLIED | SILICON | THIN BOX | well implant | MOSFETS | ENGINEERING, ELECTRICAL & ELECTRONIC | GROUND PLANE | METAL GATE | multi-V-T | Back plane (BP) | TECHNOLOGY | CMOS | Platforms | Circuit design | Threshold voltage | Devices | Channels | Digital circuits | Gates (circuits)
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17. Full Text How FD-SOI is revolutionizing next-gen microelectronics: IoT, automotive and mobile connectivity applications : ted Paper
by Nguyen, Bich-Yen and Schwarzenbach, Walter and Seller, Manuel and Flatress, Philippe and Bernard, Guillaume and Girard, Christophe and Maleville, Christophe
International Conference on Advanced Technologies for Communications, ISSN 2162-1039, 12/2018, Volume 2018-, pp. 382 - 386
buried oxide (BOX) | Fully depleted SOI | ultra-thin SOI | body biasing
Conference Proceeding
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18. Full Text Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit
by Kilchytska, V and Md Arshad, M.K and Makovejev, S and Olsen, S and Andrieu, F and Poiroux, T and Faynot, O and Raskin, J.-P and Flandre, D
Solid State Electronics, ISSN 0038-1101, 04/2012, Volume 70, pp. 50 - 58
► UTBB has a great potential for analog applications featuring high , and . ► Cut-off frequency as high as 220 GHz is achievable for 30 nm-long UTBB MOSFET. ►... 
Analog figures of merit | Cut-off frequency | Ultra-thin BOX | Output conductance | High-temperature | Ultra-thin body FD SOI MOSFETs | SIGNAL OUTPUT CONDUCTANCE | ON-NOTHING SON | PHYSICS, CONDENSED MATTER | PHYSICS, APPLIED | PERFORMANCE | BEHAVIOR | GATE | MOSFETS | ENGINEERING, ELECTRICAL & ELECTRONIC | SUBTHRESHOLD SLOPE | DEVICES | FINFETS | THRESHOLD VOLTAGE | Transistors | Complementary metal oxide semiconductors | Semiconductor industry | CMOS | Cut-off | Bias | Electronics | Benchmarking | Channels | Gain | Transconductance
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19. Full Text Fully depleted SOI (FDSOI) technology
by Cheng, Kangguo and Khakifirooz, Ali
Science China Information Sciences, ISSN 1674-733X, 6/2016, Volume 59, Issue 6, pp. 1 - 15
Fully depleted SOI (FDSOI) has become a viable technology not only for continued CMOS scaling to 22 nm node and beyond but also for improving the performances... 
foundry | strain engineering | FDSOI | Computer Science | design | low power | Information Systems and Communication Service | variability | IoT | ULTRA-THIN-BODY | COMPUTER SCIENCE, INFORMATION SYSTEMS | VLIW DSP | ENGINEERING, ELECTRICAL & ELECTRONIC | CMOS | GHZ | DEVICES | GATE LENGTH
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20. Full Text How FD-SOI is revolutionizing next-gen microelectronics: IoT, automotive and mobile connectivity applications : (Invited Paper)
by Nguyen, Bich-Yen and Schwarzenbach, Walter and Seller, Manuel and Flatress, Philippe and Bernard, Guillaume and Girard, Christophe and Maleville, Christophe
2018 International Conference on Advanced Technologies for Communications (ATC), 10/2018, pp. 382 - 386
Fully depleted silicon-on-insulator (FD-SOI) semiconductor technology enables scalability of planar semiconductors devices with unique body-bias capability.... 
Radio frequency | buried oxide (BOX) | Silicon-on-insulator | Fully depleted SOI | ultra-thin SOI | CMOS technology | Silicon | Transistors | Reliability | Substrates | body biasing
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