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time-to-digital converter (67) 67
engineering, electrical & electronic (47) 47
vernier delay line (44) 44
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1. Full Text An 802.11a/b/g/n Digital Fractional- N PLL With Automatic TDC Linearity Calibration for Spur Cancellation
by Dongyi Liao and Wang, Hechen and Dai, Fa Foster and Yang Xu and Berenguer, Roc and Hermoso, Sara Munoz
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 05/2017, Volume 52, Issue 5, pp. 1210 - 1220
A fractional-N digital phase-locked loop (PLL) architecture with low fractional spur is presented in this paper. A 2-D Vernier time-to-digital convertor (TDC)... 
2-D Vernier | Frequency conversion | N">fractional-N | Calibration | Frequency measurement | DPLL | Phase locked loops | Linearity | multimodulus divider (MMD) | least-mean-square (LMS) filter | time-to-digital convertor (TDC) | digital calibration | Delays | Clocks | fractional-N | POWER | TIME | OSCILLATOR | CMOS TECHNOLOGY | ENGINEERING, ELECTRICAL & ELECTRONIC | FREQUENCY-SYNTHESIZER | CONVERTER
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2. Full Text CMOS time-to-digital converters for mixed-mode signal processing
by Yuan, Fei
The Journal of Engineering, ISSN 2051-3305, 4/2014, Volume 2014, Issue 4, pp. 140 - 154
This study provides an in-depth review of the principles, architectures and design techniques of CMOS time-to-digital converters (TDCs). The classification of... 
oscillators | relaxation oscillator TDC | vernier TDC | MASH TDC | flash TDC | tapped delay line TDC | ΔΣ TDC | successive approximation TDC | delay lines | CMOS time-to-digital converters | sampling TDC | time-digital conversion | direct-counter TDCs | pulse-shrinking delay line TDC | noise-shaping TDC | sigma-delta modulation | switched ring oscillator TDC | CMOS integrated circuits | cyclic pulse-shrinking TDCs | pipelined TDC | mixed-mode signal processing
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3. Full Text A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC
by Ohhata, Kenichi and Hayakawa, Daiki and Sewaki, Kenji and Imayanagida, Kento and Ueno, Kouki and Sonoda, Yuuki and Muroya, Kenichiro
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN 1063-8210, 09/2018, Volume 26, Issue 9, pp. 1777 - 1787
In this paper, we propose a time-based analog-to-digital converter (ADC) architecture combining a flash ADC and vernier time-to-digital converter (TDC) to... 
pipeline | Capacitors | Logic gates | Signal processing | subranging | CMOS technology | Calibration | Power dissipation | Time-domain analysis | time-based ADC (TB ADC) | Flash analog-to-digital converter (ADC) | vernier time-to-digital converter (TDC) | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | ENGINEERING, ELECTRICAL & ELECTRONIC | CMOS | Power consumption | Steering | Amplifiers | Analog to digital conversion | Figure of merit | Analog to digital converters
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4. Full Text A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector
by Wu, Jianxi and Deng, Wei and Chen, Zipeng and Zheng, Wei and Liu, Yibo and Wang, Shufu and Qi, Nan and Chi, Baoyong
IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 10/2019, pp. 1 - 14
A 77-GHz frequency-modulated continuous-wave (FMCW) generator is presented for millimeter-wave (mm-wave) radar applications. The FMCW chirp is provided by a... 
Chirp | Image edge detection | Millimeter-wave (mm-wave) radar | Frequency conversion | frequency- modulated continuous-wave (FMCW) | segmented digital-to-analog converter (DAC) | Generators | Phase locked loops | phase-locked loop (PLL) | divider-less | glitch | Detectors | Delays | Vernier time-to-digital converter (TDC)
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5. Full Text A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique
by Nguyen, Van Nhan and Duong, Duc Nha and Chung, Yunmo and Lee, Jong-Wook
Sensors (Basel, Switzerland), ISSN 1424-8220, 11/2018, Volume 18, Issue 11, p. 3948
Herein, we present a low-power cyclic Vernier two-step time-to-digital converter (TDC) that achieves a wide input range with good linearity. Since traditional... 
Vernier | time-to-digital converter | startup time | digitally controlled oscillator | time-of-flight | cyclic | input range | ELECTROCHEMISTRY | CHEMISTRY, ANALYTICAL | INSTRUMENTS & INSTRUMENTATION | TO-DIGITAL CONVERTER | ARRAYS
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6. Full Text A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library
by Youngmin Park and Wentzloff, D. D
IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 07/2011, Volume 58, Issue 7, pp. 1511 - 1517
This paper presents a cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs), targeted for a synthesizable all-digital... 
synthesis | Vernier | All-digital PLL (ADPLL) | time-to-digital converter (TDC) | Image edge detection | Microprocessors | Layout | Computer architecture | standard cell library | Time measurement | Libraries | Calibration | CMOS | TO-DIGITAL CONVERTER | OSCILLATOR | ENGINEERING, ELECTRICAL & ELECTRONIC | Measurement | Technology application | Phase-locked loops | Oscillators (Electronics) | Circuit design | Analysis | Voltage | Design and construction | Methods | Complementary metal oxide semiconductors | Design engineering | Circuits | Digital | Phase locked loops | Oscillators | Standards
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7. Full Text Embedded Vernier TDC with sub-nano second resolution using fractional-N PLL
by Bengtsson, Lars and Naturvetenskapliga fakulteten and Institutionen för fysik (GU) and Faculty of Sciences and Göteborgs universitet and Gothenburg University and Department of Physics (GU)
Measurement, ISSN 0263-2241, 10/2017, Volume 108, pp. 48 - 54
A novel implementation technique for Vernier-based time-to-digital converters is reported. It is based on fractional- phase-locked loops which allows the... 
Vernier | FPGA | Fractional-N PLL | Phase-locked loop | Time-to-digital converter | TO-DIGITAL CONVERTER | RING OSCILLATOR TDC | TIME | METASTABILITY | CMOS | INSTRUMENTS & INSTRUMENTATION | ENGINEERING, MULTIDISCIPLINARY | FLIP-FLOPS | Digital integrated circuits | Time-to-digital converter; Phase-locked loop; Vernier; FPGA; Fractional-N PLL | Other Electrical Engineering, Electronic Engineering, Information Engineering | Acceleratorfysik och instrumentering | Inbäddad systemteknik | Accelerator Physics and Instrumentation | Signalbehandling | Embedded Systems | Signal Processing | Annan elektroteknik och elektronik
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8. Full Text Synthesizable 2D Vernier TDC based on gated ring oscillators
by Jurgo, Marijan and Navickas, Romualdas
Informacije MIDEM, ISSN 0352-9045, 12/2017, Volume 47, Issue 4, pp. 223 - 231
Time to digital converter (TDC) is a device, which measures time interval between two edges of signals and converts it to digital code. Lately it is used as... 
Vernier | CMOS | Time to digital converter | Gated ring oscillator | Integrated circuit | time to digital converter | MATERIALS SCIENCE, MULTIDISCIPLINARY | RESOLUTION | TO-DIGITAL CONVERTER | gated ring oscillator | integrated circuit | PHASE-LOCKED LOOP | ENGINEERING, ELECTRICAL & ELECTRONIC
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9. Full Text Widening and narrowing of time interval due to single-event transients in 45nm vernier-type TDC
by Ramaniharan, PK and Boby, B
IET CIRCUITS DEVICES & SYSTEMS, ISSN 1751-858X, 11/2017, Volume 11, Issue 6, pp. 676 - 681
Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in sub-100nm regime in radiation environment.... 
staircase transfer characteristics | SET | TO-DIGITAL CONVERTER | space applications | priority encoder | time-digital conversion | electronic component | time-to-digital converter | time interval | size 45 nm | D-flip-flop | VCDL | single-event transients | radiation environment | guard gate technique | vernier-type TDC | START-STOP pulse transition | radiation hardening (electronics) | SIMULATION | cadence spectre circuit simulator | ENGINEERING, ELECTRICAL & ELECTRONIC | delay lines | HIS | HIGH-RESOLUTION | heavy-ion strikes | PROPAGATION | top-bottom voltage-controlled delay line | regular staircase pattern
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10. Full Text The Soft-Injection-Locked Ring Oscillator and Its Application in a Vernier-Based TDC
by Yao, Chia-Yu and Hsia, Wei-Chun and Wen, Yu-Jou
IEEE Transactions on Instrumentation and Measurement, ISSN 0018-9456, 08/2014, Volume 63, Issue 8, pp. 2064 - 2071
A time-to-digital converter (TDC) plays an important role in time interval measurement. Among various TDC structures, the Vernier-based TDC (VTDC) is promising... 
Differential nonlinearity (DNL) | time-to-digital converter (TDC) | Radiation detectors | Image edge detection | Vernier-based TDC (VTDC) | Resonant frequency | soft-injection-locked ring (SILR) oscillators | Tin | integral nonlinearity (INL) | Oscillators | Clocks | INSTRUMENTS & INSTRUMENTATION | TO-DIGITAL CONVERTER | ENGINEERING, ELECTRICAL & ELECTRONIC | Digital control systems | Usage | Time measurement | Oscillators (Electronics) | Timekeeping | Analysis | CMOS | Electric potential | Voltage | Instrumentation | Nonlinearity | Calibration | Deviation
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11. Full Text Analysis and Correction of Noise Injection Due to Parallel-Output-Misalignment (POM) Effects in Ring-Type Time-to-Digital Converters (TDCs)
by Wang, Tuoxin and Rogers, John W. M and Mitric, Krste
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 09/2019, Volume 54, Issue 9, pp. 2513 - 2522
A phenomenon called parallel-output misalignment (POM), which intrinsically occurs in ring-type time-to-digital converters (TDCs) like gated-ring oscillator... 
Phase noise | parallel-output misalignment (POM) | Quantization (signal) | time-to-digital converter (TDC) | digital phase-locked loop (DPLL) | Logic gates | Delays | Error correction | Conjoined-ring Vernier (CRV) | PLL | RESOLUTION | phase noise | ENGINEERING, ELECTRICAL & ELECTRONIC
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12. Full Text A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order \Delta \Sigma Linearization
by Hechen Wang and Dai, Fa Foster and Hua Wang
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 03/2018, Volume 53, Issue 3, pp. 738 - 749
This paper presents an 8-bit 1.25-ps resolution reconfigurable Vernier time-to-digital converter (TDC) with a 2-D spiral comparator array and ΔΣ modulators for... 
Phase noise | Spirals | Phase modulation | ΔΣ modulation | autocalibration | integral nonlinearity (INL) | Topology | differential nonlinearity (DNL) | time-to-digital converter (TDC) | Measurement uncertainty | digital phase-locked loop (DPLL) | Linearity | Vernier TDC | Delays | linearization | ENGINEERING, ELECTRICAL & ELECTRONIC | N FREQUENCY-SYNTHESIZER | CMOS | PLL | TRANSMITTER | TDC | Delta Sigma modulation | Converters | Nonlinearity | Power consumption | Modulators | Linearization
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13. Full Text A 15b, Sub-10ps resolution, low dead time, wide range two-stage TDC
by Narku-Tetteh, Noble and Titriku, Alex and Palermo, Samuel
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), ISSN 1548-3746, 08/2014, pp. 13 - 16
Advancements in imaging and ranging system performance creates the need for increased resolution, range, and speed of time-to-digital converters, a core part... 
Image resolution | Radiation detectors | Dynamic range | Signal resolution | Vernier delay loop | positron-emission tomography (PET) | Quantization (signal) | TDC | coarse-fine architecture | Delay lines | time-of-flight (ToF) | laser/light detection and ranging (LIDAR) | Delays | CMOS | Circuits | Imaging | Converters | Sampling | Conversion | Delay | Coarsening | Clocks
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14. A low dead time vernier delay line TDC implemented in an actel flash-based FPGA
by Qin, Xi and Feng, Changqing and Zhang, Deliang and Zhao, Lei and Liu, Shubin and An, Qi
Nuclear Science and Techniques, ISSN 1001-8042, 08/2013, Volume 24, Issue 4
In this paper, a high precision vernier delay line (VDL) TDC (Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is... 
Vernier | Time measurement | Double delay lines | Time-to-digital convertor | Compensation | SYSTEM | PROGRAMMABLE-GATE-ARRAYS | NUCLEAR SCIENCE & TECHNOLOGY | RESOLUTION | TO-DIGITAL CONVERTER | PHYSICS, NUCLEAR
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15. Full Text A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
by Andersson, Niklas U and Vesterbacka, Mark and Linköpings universitet and Tekniska högskolan and Institutionen för systemteknik and Elektroniska Kretsar och System
IEEE Transactions on Circuits and Systems II: Express Briefs, ISSN 1549-7747, 10/2014, Volume 61, Issue 10, pp. 773 - 777
A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the... 
Latches | Power demand | Delay lines | Delays | CMOS integrated circuits | Transistors | Standards | Vernier | CMOS | Delay latch | Time-to-digital converter (TDC) | TDC | time-to-digital converter (TDC) | 90 NM CMOS | RESOLUTION | delay latch | ENGINEERING, ELECTRICAL & ELECTRONIC | Measurement | Usage | Digital integrated circuits | Voltage | Design and construction | Complementary metal oxide semiconductors | Analog to digital converters | Architecture | Converters | Chains | Digital | Registers | Delay | Teknik och teknologier | Engineering and Technology | Elektroteknik och elektronik | Electrical Engineering, Electronic Engineering, Information Engineering | CMOS; delay latch; time-to-digital converter (TDC); Vernier
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16. Full Text A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation
by Markovic, B and Tisa, S and Villa, F. A and Tosi, A and Zappa, F
IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, 03/2013, Volume 60, Issue 3, pp. 557 - 569
This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-precision and high-linearity with moderate area occupation per... 
Coarse-fine architecture | delay-locked loop (DLL) | Radiation detectors | TCSPC | single photon avalanche diode (SPAD) | Synchronization | Delay | Interpolation | time-to-digital converter (TDC) | Linearity | time-of-flight | Clocks | time interval measurement | Vernier delay line | CMOS TIME | ANALOG | FREQUENCY-SYNTHESIS | ENGINEERING, ELECTRICAL & ELECTRONIC | CIRCUITS | TDC | HIGH-RESOLUTION | Technology application | Usage | Signal processing | Photodetectors | Equipment and supplies | Design and construction | Complementary metal oxide semiconductors | Electronic circuits | Studies | Sensors | Architecture | Circuits | Converters | Channels | Three dimensional
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17. Full Text Two-Dimensions Vernier Time-to-Digital Converter
by Vercesi, Luca and Liscidini, Antonio and Castello, Rinaldo
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 08/2010, Volume 45, Issue 8, pp. 1504 - 1512
A two-dimensions Vernier algorithm applied to a time to digital converter (TDC) is presented. The solution proposed minimizes the length of the delay lines... 
Phase noise | Vernier | Energy consumption | TDC calibration | time to digital converter | Delay effects | Quantization | Jitter | Phase locked loops | Interpolation | Prototypes | Delay lines | CMOS technology | All digital PLL | CMOS | PLL | TDC | ENGINEERING, ELECTRICAL & ELECTRONIC | Power consumption | Converters | Digital | Two dimensional | Conversion
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18. Full Text A 12-Bit vernier ring time-to-digital converter in 0.13 μ CMOS technology
by Yu, Jianjun and Dai, Fa Foster and Jaeger, Richard C
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 04/2010, Volume 45, Issue 4, pp. 830 - 842
Vernier | Frequency synthesis | Digital phase locked loop (DPLL) | Time-to-digital converter (TDC) | Time and phase measurement
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19. Full Text A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques
by Temporiti, E and Weltin-Wu, C and Baldi, D and Tonietto, R and Svelto, F
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 03/2009, Volume 44, Issue 3, pp. 824 - 834
Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly,... 
Frequency synthesizers | all-digital phase locked loop | Quantization | CMOS process | Phase locked loops | mismatch correction | Radio frequency | Low voltage | time-to-digital converter (TDC) | Linearity | Bandwidth | spur reduction | Vernier TDC | CMOS technology | ADPLL | digital calibration | fractional frequency synthesizer | Wideband | Mismatch correction | All-digital phase locked loop | Fractional frequency synthesizer | Time-to-digital converter (TDC) | Spur reduction | Digital calibration | PHASE-LOCKED LOOPS | CONVERTER | ENGINEERING, ELECTRICAL & ELECTRONIC | Semiconductors | Consumption | CMOS | Electric potential | Reduction | Chips
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20. Full Text A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion
by Henzler, S and Koeppe, S and Lorenz, D and Kamp, W and Kuenemund, R and Schmitt-Landsiedel, D
IEEE Journal of Solid-State Circuits, ISSN 0018-9200, 07/2008, Volume 43, Issue 7, pp. 1666 - 1676
Time-to-digital converters (TDCs) are promising building blocks for the digitalization of mixed-signal functionality in ultra-deep-submicron CMOS technologies.... 
Phase measurement | Circuits | Phase locked loops | Delay | Signal resolution | Digital calibration | Interpolation | pulse shrinking | time-to-digital converter (TDC) | passive time interpolation | Voltage | Vernier TDC | CMOS technology | digital PLL | Velocity measurement | high-resolution time interval measurement | Signal to noise ratio | High-resolution time interval measurement | Pulse shrinking | Digital PLL | Time-to-digital converter (TDC) | Passive time interpolation | CMOS | digital calibration | CONVERTER | ENGINEERING, ELECTRICAL & ELECTRONIC | Construction | State of the art | Quantization | Voltage dividers | Nonlinearity | Inverters | Coarsening
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